diff options
| author | Stephen Hines <srhines@google.com> | 2014-04-23 16:57:46 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-04-24 15:53:16 -0700 |
| commit | 36b56886974eae4f9c5ebc96befd3e7bfe5de338 (patch) | |
| tree | e6cfb69fbbd937f450eeb83bfb83b9da3b01275a /test/CodeGen/PowerPC/crbit-asm.ll | |
| parent | 69a8640022b04415ae9fac62f8ab090601d8f889 (diff) | |
| download | external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.zip external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.tar.gz external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.tar.bz2 | |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
Diffstat (limited to 'test/CodeGen/PowerPC/crbit-asm.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/crbit-asm.ll | 59 |
1 files changed, 59 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/crbit-asm.ll b/test/CodeGen/PowerPC/crbit-asm.ll new file mode 100644 index 0000000..373e334 --- /dev/null +++ b/test/CodeGen/PowerPC/crbit-asm.ll @@ -0,0 +1,59 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define zeroext i1 @testi1(i1 zeroext %b1, i1 zeroext %b2) #0 { +entry: + %0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i1 %b1, i1 %b2) #0 + %1 = and i8 %0, 1 + %tobool3 = icmp ne i8 %1, 0 + ret i1 %tobool3 + +; CHECK-LABEL: @testi1 +; CHECK-DAG: andi. {{[0-9]+}}, 3, 1 +; CHECK-DAG: li [[REG1:[0-9]+]], 0 +; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1 +; CHECK-DAG: andi. {{[0-9]+}}, 4, 1 +; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1 +; CHECK-DAG: li [[REG4:[0-9]+]], 1 +; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]] +; CHECK: blr +} + +define signext i32 @testi32(i32 signext %b1, i32 signext %b2) #0 { +entry: + %0 = tail call i32 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i32 %b1, i32 %b2) #0 + ret i32 %0 + +; The ABI sign_extend should combine with the any_extend from the asm result, +; and the result will be 0 or -1. This highlights the fact that only the first +; bit is meaningful. +; CHECK-LABEL: @testi32 +; CHECK-DAG: andi. {{[0-9]+}}, 3, 1 +; CHECK-DAG: li [[REG1:[0-9]+]], 0 +; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1 +; CHECK-DAG: andi. {{[0-9]+}}, 4, 1 +; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1 +; CHECK-DAG: li [[REG4:[0-9]+]], -1 +; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]] +; CHECK: blr +} + +define zeroext i8 @testi8(i8 zeroext %b1, i8 zeroext %b2) #0 { +entry: + %0 = tail call i8 asm "crand $0, $1, $2", "=^wc,^wc,^wc"(i8 %b1, i8 %b2) #0 + ret i8 %0 + +; CHECK-LABEL: @testi8 +; CHECK-DAG: andi. {{[0-9]+}}, 3, 1 +; CHECK-DAG: li [[REG1:[0-9]+]], 0 +; CHECK-DAG: cror [[REG2:[0-9]+]], 1, 1 +; CHECK-DAG: andi. {{[0-9]+}}, 4, 1 +; CHECK-DAG: crand [[REG3:[0-9]+]], [[REG2]], 1 +; CHECK-DAG: li [[REG4:[0-9]+]], 1 +; CHECK: isel 3, [[REG4]], [[REG1]], [[REG3]] +; CHECK: blr +} + +attributes #0 = { nounwind } + |