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author | Hal Finkel <hfinkel@anl.gov> | 2013-04-09 22:58:37 +0000 |
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committer | Hal Finkel <hfinkel@anl.gov> | 2013-04-09 22:58:37 +0000 |
commit | 7eb0d8148e1210d9e31ab471477de47b53bab117 (patch) | |
tree | 59cbf016ac5c78bc44d43e66bc48073584217500 /test/CodeGen/PowerPC/early-ret2.ll | |
parent | 58ddf528927a57c4f92ef12513bfef3422318b77 (diff) | |
download | external_llvm-7eb0d8148e1210d9e31ab471477de47b53bab117.zip external_llvm-7eb0d8148e1210d9e31ab471477de47b53bab117.tar.gz external_llvm-7eb0d8148e1210d9e31ab471477de47b53bab117.tar.bz2 |
Allow PPC B and BLR to be if-converted into some predicated forms
This enables us to form predicated branches (which are the same conditional
branches we had before) and also a larger set of predicated returns (including
instructions like bdnzlr which is a conditional return and loop-counter
decrement all in one).
At the moment, if conversion does not capture all possible opportunities. A
simple example is provided in early-ret2.ll, where if conversion forms one
predicated return, and then the PPCEarlyReturn pass picks up the other one. So,
at least for now, we'll keep both mechanisms.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179134 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/early-ret2.ll')
-rw-r--r-- | test/CodeGen/PowerPC/early-ret2.ll | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/early-ret2.ll b/test/CodeGen/PowerPC/early-ret2.ll new file mode 100644 index 0000000..bedd16c --- /dev/null +++ b/test/CodeGen/PowerPC/early-ret2.ll @@ -0,0 +1,26 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define void @_Z8example3iPiS_() #0 { +entry: + br i1 undef, label %while.end, label %while.body.lr.ph + +while.body.lr.ph: ; preds = %entry + br i1 undef, label %while.end, label %while.body + +while.body: ; preds = %while.body, %while.body.lr.ph + br i1 false, label %while.end, label %while.body, !llvm.vectorizer.already_vectorized !0 + +while.end: ; preds = %while.body, %while.body.lr.ph, %entry + ret void + +; CHECK: @_Z8example3iPiS_ +; CHECK: bnelr +; CHECK: bnelr +} + +attributes #0 = { noinline nounwind } + +!0 = metadata !{} + |