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author | Pirama Arumuga Nainar <pirama@google.com> | 2015-05-06 11:46:36 -0700 |
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committer | Pirama Arumuga Nainar <pirama@google.com> | 2015-05-18 10:52:30 -0700 |
commit | 2c3e0051c31c3f5b2328b447eadf1cf9c4427442 (patch) | |
tree | c0104029af14e9f47c2ef58ca60e6137691f3c9b /test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll | |
parent | e1bc145815f4334641be19f1c45ecf85d25b6e5a (diff) | |
download | external_llvm-2c3e0051c31c3f5b2328b447eadf1cf9c4427442.zip external_llvm-2c3e0051c31c3f5b2328b447eadf1cf9c4427442.tar.gz external_llvm-2c3e0051c31c3f5b2328b447eadf1cf9c4427442.tar.bz2 |
Update aosp/master LLVM for rebase to r235153
Change-Id: I9bf53792f9fc30570e81a8d80d296c681d005ea7
(cherry picked from commit 0c7f116bb6950ef819323d855415b2f2b0aad987)
Diffstat (limited to 'test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll')
-rw-r--r-- | test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll | 15 |
1 files changed, 5 insertions, 10 deletions
diff --git a/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll b/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll index ab439cd..8a873da 100644 --- a/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll +++ b/test/CodeGen/PowerPC/fast-isel-load-store-vsx.ll @@ -1,15 +1,12 @@ -;; There are some known limitations in the VSX support during FastIsel -;; (see fast-isel-load-store.ll header). Nevertheless, we are adding some -;; regressions here for bugs we fix in the meantime ; RUN: llc < %s -O0 -fast-isel -mattr=+vsx -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64VSX ;; The semantics of VSX stores for when R0 is used is different depending on ;; whether it is used as base or offset. If used as base, the effective -;; address computation will use zero regardless the content of R0. If used as -;; offset, the content will be used in the effective address. We observed that +;; address computation will use zero regardless of the content of R0. If used as +;; an offset the content will be used in the effective address. We observed that ;; for some constructors, the initialization values were being stored without -;; any offset register being specified which was causing R0 to be used as offset -;; in regions where it contained the value in the link register. This regression +;; an offset register being specified which was causing R0 to be used as offset +;; in regions where it contained the value in the link register. This test ;; verifies that R0 is used as base in these situations. %SomeStruct = type { double } @@ -28,6 +25,4 @@ entry: %0 = load double, double* %V.addr, align 8 store double %0, double* %Val, align 8 ret void - } - - + } |