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| author | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2013-08-30 02:43:08 +0000 |
|---|---|---|
| committer | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2013-08-30 02:43:08 +0000 |
| commit | 118eb5894e448dfddc0152f8f28284315b6f955e (patch) | |
| tree | 06045d81b299301cf200d00f1f82f757dd0727e4 /test/CodeGen/PowerPC/fast-isel-shifter.ll | |
| parent | 7248968fa529726b44d41bd25403d50c74db4bc4 (diff) | |
| download | external_llvm-118eb5894e448dfddc0152f8f28284315b6f955e.zip external_llvm-118eb5894e448dfddc0152f8f28284315b6f955e.tar.gz external_llvm-118eb5894e448dfddc0152f8f28284315b6f955e.tar.bz2 | |
[PowerPC] Miscellaneous fast-isel test cases.
Here are a few more tests that now pass after the recent fast-isel
commits.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189637 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/fast-isel-shifter.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/fast-isel-shifter.ll | 50 |
1 files changed, 50 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/fast-isel-shifter.ll b/test/CodeGen/PowerPC/fast-isel-shifter.ll new file mode 100644 index 0000000..198bfbe --- /dev/null +++ b/test/CodeGen/PowerPC/fast-isel-shifter.ll @@ -0,0 +1,50 @@ +; RUN: llc < %s -O0 -verify-machineinstrs -fast-isel-abort -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s --check-prefix=ELF64 + +define i32 @shl() nounwind ssp { +entry: +; ELF64: shl +; ELF64: slw + %shl = shl i32 -1, 2 + ret i32 %shl +} + +define i32 @shl_reg(i32 %src1, i32 %src2) nounwind ssp { +entry: +; ELF64: shl_reg +; ELF64: slw + %shl = shl i32 %src1, %src2 + ret i32 %shl +} + +define i32 @lshr() nounwind ssp { +entry: +; ELF64: lshr +; ELF64: srw + %lshr = lshr i32 -1, 2 + ret i32 %lshr +} + +define i32 @lshr_reg(i32 %src1, i32 %src2) nounwind ssp { +entry: +; ELF64: lshr_reg +; ELF64: srw + %lshr = lshr i32 %src1, %src2 + ret i32 %lshr +} + +define i32 @ashr() nounwind ssp { +entry: +; ELF64: ashr +; ELF64: srawi + %ashr = ashr i32 -1, 2 + ret i32 %ashr +} + +define i32 @ashr_reg(i32 %src1, i32 %src2) nounwind ssp { +entry: +; ELF64: ashr_reg +; ELF64: sraw + %ashr = ashr i32 %src1, %src2 + ret i32 %ashr +} + |