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| author | Stephen Hines <srhines@google.com> | 2014-04-23 16:57:46 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-04-24 15:53:16 -0700 |
| commit | 36b56886974eae4f9c5ebc96befd3e7bfe5de338 (patch) | |
| tree | e6cfb69fbbd937f450eeb83bfb83b9da3b01275a /test/CodeGen/PowerPC/float-to-int.ll | |
| parent | 69a8640022b04415ae9fac62f8ab090601d8f889 (diff) | |
| download | external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.zip external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.tar.gz external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.tar.bz2 | |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
Diffstat (limited to 'test/CodeGen/PowerPC/float-to-int.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/float-to-int.ll | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/float-to-int.ll b/test/CodeGen/PowerPC/float-to-int.ll index 39cd4f9..9c897cb 100644 --- a/test/CodeGen/PowerPC/float-to-int.ll +++ b/test/CodeGen/PowerPC/float-to-int.ll @@ -1,4 +1,5 @@ ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck %s +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx | FileCheck -check-prefix=CHECK-VSX %s ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -12,6 +13,12 @@ define i64 @foo(float %a) nounwind { ; CHECK: stfd [[REG]], ; CHECK: ld 3, ; CHECK: blr + +; CHECK-VSX: @foo +; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 1 +; CHECK-VSX: stxsdx [[REG]], +; CHECK-VSX: ld 3, +; CHECK-VSX: blr } define i64 @foo2(double %a) nounwind { @@ -23,6 +30,12 @@ define i64 @foo2(double %a) nounwind { ; CHECK: stfd [[REG]], ; CHECK: ld 3, ; CHECK: blr + +; CHECK-VSX: @foo2 +; CHECK-VSX: xscvdpsxds [[REG:[0-9]+]], 1 +; CHECK-VSX: stxsdx [[REG]], +; CHECK-VSX: ld 3, +; CHECK-VSX: blr } define i64 @foo3(float %a) nounwind { @@ -34,6 +47,12 @@ define i64 @foo3(float %a) nounwind { ; CHECK: stfd [[REG]], ; CHECK: ld 3, ; CHECK: blr + +; CHECK-VSX: @foo3 +; CHECK-VSX: xscvdpuxds [[REG:[0-9]+]], 1 +; CHECK-VSX: stxsdx [[REG]], +; CHECK-VSX: ld 3, +; CHECK-VSX: blr } define i64 @foo4(double %a) nounwind { @@ -45,6 +64,12 @@ define i64 @foo4(double %a) nounwind { ; CHECK: stfd [[REG]], ; CHECK: ld 3, ; CHECK: blr + +; CHECK-VSX: @foo4 +; CHECK-VSX: xscvdpuxds [[REG:[0-9]+]], 1 +; CHECK-VSX: stxsdx [[REG]], +; CHECK-VSX: ld 3, +; CHECK-VSX: blr } define i32 @goo(float %a) nounwind { @@ -56,6 +81,12 @@ define i32 @goo(float %a) nounwind { ; CHECK: stfiwx [[REG]], ; CHECK: lwz 3, ; CHECK: blr + +; CHECK-VSX: @goo +; CHECK-VSX: xscvdpsxws [[REG:[0-9]+]], 1 +; CHECK-VSX: stfiwx [[REG]], +; CHECK-VSX: lwz 3, +; CHECK-VSX: blr } define i32 @goo2(double %a) nounwind { @@ -67,6 +98,12 @@ define i32 @goo2(double %a) nounwind { ; CHECK: stfiwx [[REG]], ; CHECK: lwz 3, ; CHECK: blr + +; CHECK-VSX: @goo2 +; CHECK-VSX: xscvdpsxws [[REG:[0-9]+]], 1 +; CHECK-VSX: stfiwx [[REG]], +; CHECK-VSX: lwz 3, +; CHECK-VSX: blr } define i32 @goo3(float %a) nounwind { @@ -78,6 +115,12 @@ define i32 @goo3(float %a) nounwind { ; CHECK: stfiwx [[REG]], ; CHECK: lwz 3, ; CHECK: blr + +; CHECK-VSX: @goo3 +; CHECK-VSX: xscvdpuxws [[REG:[0-9]+]], 1 +; CHECK-VSX: stfiwx [[REG]], +; CHECK-VSX: lwz 3, +; CHECK-VSX: blr } define i32 @goo4(double %a) nounwind { @@ -89,5 +132,11 @@ define i32 @goo4(double %a) nounwind { ; CHECK: stfiwx [[REG]], ; CHECK: lwz 3, ; CHECK: blr + +; CHECK-VSX: @goo4 +; CHECK-VSX: xscvdpuxws [[REG:[0-9]+]], 1 +; CHECK-VSX: stfiwx [[REG]], +; CHECK-VSX: lwz 3, +; CHECK-VSX: blr } |