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| author | Hal Finkel <hfinkel@anl.gov> | 2013-04-01 17:52:07 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-04-01 17:52:07 +0000 |
| commit | 46479197843ecb651adc9417c49bbd1b00acfcb6 (patch) | |
| tree | 143df888333c2baabf6cf07c8ef7297b86b5035c /test/CodeGen/PowerPC/float-to-int.ll | |
| parent | a1f4290ac94f34173e3561c717390de07dccc646 (diff) | |
| download | external_llvm-46479197843ecb651adc9417c49bbd1b00acfcb6.zip external_llvm-46479197843ecb651adc9417c49bbd1b00acfcb6.tar.gz external_llvm-46479197843ecb651adc9417c49bbd1b00acfcb6.tar.bz2 | |
Add more PPC floating-point conversion instructions
The P7 and A2 have additional floating-point conversion instructions which
allow a direct two-instruction sequence (plus load/store) to convert from all
combinations (signed/unsigned i32/i64) <--> (float/double) (on previous cores,
only some combinations were directly available).
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178480 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/float-to-int.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/float-to-int.ll | 92 |
1 files changed, 92 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/float-to-int.ll b/test/CodeGen/PowerPC/float-to-int.ll new file mode 100644 index 0000000..ebd0903 --- /dev/null +++ b/test/CodeGen/PowerPC/float-to-int.ll @@ -0,0 +1,92 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define i64 @foo(float %a) nounwind { + %x = fptosi float %a to i64 + ret i64 %x + +; CHECK: @foo +; CHECK: fctidz [[REG:[0-9]+]], 1 +; CHECK: stfd [[REG]], +; CHECK: ld 3, +; CHECK: blr +} + +define i64 @foo2(double %a) nounwind { + %x = fptosi double %a to i64 + ret i64 %x + +; CHECK: @foo2 +; CHECK: fctidz [[REG:[0-9]+]], 1 +; CHECK: stfd [[REG]], +; CHECK: ld 3, +; CHECK: blr +} + +define i64 @foo3(float %a) nounwind { + %x = fptoui float %a to i64 + ret i64 %x + +; CHECK: @foo3 +; CHECK: fctiduz [[REG:[0-9]+]], 1 +; CHECK: stfd [[REG]], +; CHECK: ld 3, +; CHECK: blr +} + +define i64 @foo4(double %a) nounwind { + %x = fptoui double %a to i64 + ret i64 %x + +; CHECK: @foo4 +; CHECK: fctiduz [[REG:[0-9]+]], 1 +; CHECK: stfd [[REG]], +; CHECK: ld 3, +; CHECK: blr +} + +define i32 @goo(float %a) nounwind { + %x = fptosi float %a to i32 + ret i32 %x + +; CHECK: @goo +; CHECK: fctiwz [[REG:[0-9]+]], 1 +; CHECK: stfiwx [[REG]], +; CHECK: lwz 3, +; CHECK: blr +} + +define i32 @goo2(double %a) nounwind { + %x = fptosi double %a to i32 + ret i32 %x + +; CHECK: @goo2 +; CHECK: fctiwz [[REG:[0-9]+]], 1 +; CHECK: stfiwx [[REG]], +; CHECK: lwz 3, +; CHECK: blr +} + +define i32 @goo3(float %a) nounwind { + %x = fptoui float %a to i32 + ret i32 %x + +; CHECK: @goo3 +; CHECK: fctiwuz [[REG:[0-9]+]], 1 +; CHECK: stfiwx [[REG]], +; CHECK: lwz 3, +; CHECK: blr +} + +define i32 @goo4(double %a) nounwind { + %x = fptoui double %a to i32 + ret i32 %x + +; CHECK: @goo4 +; CHECK: fctiwuz [[REG:[0-9]+]], 1 +; CHECK: stfiwx [[REG]], +; CHECK: lwz 3, +; CHECK: blr +} + |