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| author | Hal Finkel <hfinkel@anl.gov> | 2013-03-31 01:58:02 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-03-31 01:58:02 +0000 |
| commit | 9ad0f4907b3ba0916a8b6cdb95d298d2ddb7d405 (patch) | |
| tree | 95b16c768d1a5e1d043d3459b352fd34a665076b /test/CodeGen/PowerPC/i32-to-float.ll | |
| parent | 0b68b758bbb6718fc67423109eeb9df64c711a37 (diff) | |
| download | external_llvm-9ad0f4907b3ba0916a8b6cdb95d298d2ddb7d405.zip external_llvm-9ad0f4907b3ba0916a8b6cdb95d298d2ddb7d405.tar.gz external_llvm-9ad0f4907b3ba0916a8b6cdb95d298d2ddb7d405.tar.bz2 | |
Cleanup PPC(64) i32 -> float/double conversion
The existing SINT_TO_FP code for i32 -> float/double conversion was disabled
because it relied on broken EXTSW_32/STD_32 instruction definitions. The
original intent had been to enable these 64-bit instructions to be used on CPUs
that support them even in 32-bit mode. Unfortunately, this form of lying to
the infrastructure was buggy (as explained in the FIXME comment) and had
therefore been disabled.
This re-enables this functionality, using regular DAG nodes, but only when
compiling in 64-bit mode. The old STD_32/EXTSW_32 definitions (which were dead)
are removed.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178438 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/i32-to-float.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/i32-to-float.ll | 31 |
1 files changed, 31 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/i32-to-float.ll b/test/CodeGen/PowerPC/i32-to-float.ll new file mode 100644 index 0000000..0807717 --- /dev/null +++ b/test/CodeGen/PowerPC/i32-to-float.ll @@ -0,0 +1,31 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define float @foo(i32 %a) nounwind { +entry: + %x = sitofp i32 %a to float + ret float %x + +; CHECK: @foo +; CHECK: extsw [[REG:[0-9]+]], 3 +; CHECK: std [[REG]], +; CHECK: lfd [[REG2:[0-9]+]], +; CHECK: fcfid [[REG3:[0-9]+]], [[REG2]] +; CHECK: frsp 1, [[REG3]] +; CHECK: blr +} + +define double @goo(i32 %a) nounwind { +entry: + %x = sitofp i32 %a to double + ret double %x + +; CHECK: @goo +; CHECK: extsw [[REG:[0-9]+]], 3 +; CHECK: std [[REG]], +; CHECK: lfd [[REG2:[0-9]+]], +; CHECK: fcfid 1, [[REG2]] +; CHECK: blr +} + |