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| author | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2013-02-21 17:12:27 +0000 |
|---|---|---|
| committer | Bill Schmidt <wschmidt@linux.vnet.ibm.com> | 2013-02-21 17:12:27 +0000 |
| commit | 53b0b0e75480121e4e01a7a76e17909e92b1762a (patch) | |
| tree | a42c57c8f06d3b753eb8d75f2feb91711c505194 /test/CodeGen/PowerPC/mcm-3.ll | |
| parent | f6c80bde655c1f08f7a42a55150727b0a7fad65d (diff) | |
| download | external_llvm-53b0b0e75480121e4e01a7a76e17909e92b1762a.zip external_llvm-53b0b0e75480121e4e01a7a76e17909e92b1762a.tar.gz external_llvm-53b0b0e75480121e4e01a7a76e17909e92b1762a.tar.bz2 | |
Large code model support for PowerPC.
Large code model is identical to medium code model except that the
addis/addi sequence for "local" accesses is never used. All accesses
use the addis/ld sequence.
The coding changes are straightforward; most of the patch is taken up
with creating variants of the medium model tests for large model.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175767 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/mcm-3.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/mcm-3.ll | 37 |
1 files changed, 25 insertions, 12 deletions
diff --git a/test/CodeGen/PowerPC/mcm-3.ll b/test/CodeGen/PowerPC/mcm-3.ll index 0e7bbe7..b790550 100644 --- a/test/CodeGen/PowerPC/mcm-3.ll +++ b/test/CodeGen/PowerPC/mcm-3.ll @@ -1,6 +1,7 @@ -; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=medium <%s | FileCheck -check-prefix=MEDIUM %s +; RUN: llc -mcpu=pwr7 -O0 -code-model=large <%s | FileCheck -check-prefix=LARGE %s -; Test correct code generation for medium code model (32-bit TOC offsets) +; Test correct code generation for medium and large code model ; for loading and storing a file-scope static variable. target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" @@ -16,13 +17,25 @@ entry: ret i32 %0 } -; CHECK: test_file_static: -; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha -; CHECK: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l -; CHECK: lwz {{[0-9]+}}, 0([[REG2]]) -; CHECK: stw {{[0-9]+}}, 0([[REG2]]) -; CHECK: .type [[VAR]],@object -; CHECK: .data -; CHECK: .globl [[VAR]] -; CHECK: [[VAR]]: -; CHECK: .long 5 +; MEDIUM: test_file_static: +; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha +; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l +; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]]) +; MEDIUM: stw {{[0-9]+}}, 0([[REG2]]) +; MEDIUM: .type [[VAR]],@object +; MEDIUM: .data +; MEDIUM: .globl [[VAR]] +; MEDIUM: [[VAR]]: +; MEDIUM: .long 5 + +; LARGE: test_file_static: +; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha +; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]]) +; LARGE: lwz {{[0-9]+}}, 0([[REG2]]) +; LARGE: stw {{[0-9]+}}, 0([[REG2]]) +; LARGE: .type [[VAR]],@object +; LARGE: .data +; LARGE: .globl [[VAR]] +; LARGE: [[VAR]]: +; LARGE: .long 5 + |