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| author | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-10 22:08:18 +0000 |
|---|---|---|
| committer | Android Git Automerger <android-git-automerger@android.com> | 2015-04-10 22:08:18 +0000 |
| commit | 13a7db5b9c4f5e543d037be68ec3428216bfd550 (patch) | |
| tree | 1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/CodeGen/PowerPC/mcm-5.ll | |
| parent | 0eb46f5d1e06a4284663d636a74b06adc3a161d7 (diff) | |
| parent | 31195f0bdca6ee2a5e72d07edf13e1d81206d949 (diff) | |
| download | external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.zip external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.gz external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.bz2 | |
am 31195f0b: Merge "Update aosp/master llvm for rebase to r233350"
* commit '31195f0bdca6ee2a5e72d07edf13e1d81206d949':
Update aosp/master llvm for rebase to r233350
Diffstat (limited to 'test/CodeGen/PowerPC/mcm-5.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/mcm-5.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/CodeGen/PowerPC/mcm-5.ll b/test/CodeGen/PowerPC/mcm-5.ll index 92ddeca..0c25845 100644 --- a/test/CodeGen/PowerPC/mcm-5.ll +++ b/test/CodeGen/PowerPC/mcm-5.ll @@ -11,7 +11,7 @@ define signext i32 @test_jump_table(i32 signext %i) nounwind { entry: %i.addr = alloca i32, align 4 store i32 %i, i32* %i.addr, align 4 - %0 = load i32* %i.addr, align 4 + %0 = load i32, i32* %i.addr, align 4 switch i32 %0, label %sw.default [ i32 3, label %sw.bb i32 4, label %sw.bb1 @@ -23,31 +23,31 @@ sw.default: ; preds = %entry br label %sw.epilog sw.bb: ; preds = %entry - %1 = load i32* %i.addr, align 4 + %1 = load i32, i32* %i.addr, align 4 %mul = mul nsw i32 %1, 7 store i32 %mul, i32* %i.addr, align 4 br label %sw.bb1 sw.bb1: ; preds = %entry, %sw.bb - %2 = load i32* %i.addr, align 4 + %2 = load i32, i32* %i.addr, align 4 %dec = add nsw i32 %2, -1 store i32 %dec, i32* %i.addr, align 4 br label %sw.bb2 sw.bb2: ; preds = %entry, %sw.bb1 - %3 = load i32* %i.addr, align 4 + %3 = load i32, i32* %i.addr, align 4 %add = add nsw i32 %3, 3 store i32 %add, i32* %i.addr, align 4 br label %sw.bb3 sw.bb3: ; preds = %entry, %sw.bb2 - %4 = load i32* %i.addr, align 4 + %4 = load i32, i32* %i.addr, align 4 %shl = shl i32 %4, 1 store i32 %shl, i32* %i.addr, align 4 br label %sw.epilog sw.epilog: ; preds = %sw.bb3, %sw.default - %5 = load i32* %i.addr, align 4 + %5 = load i32, i32* %i.addr, align 4 ret i32 %5 } |