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| author | Hal Finkel <hfinkel@anl.gov> | 2012-08-06 21:21:44 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2012-08-06 21:21:44 +0000 |
| commit | f45717e985260e9416dbd2fe8df471d48705c86a (patch) | |
| tree | 923d6a32b94723bad2265bccd735fbea08895d62 /test/CodeGen/PowerPC/ppc64-cyclecounter.ll | |
| parent | b0f6759ab93b42570d71665b13d24ca2c4a5f276 (diff) | |
| download | external_llvm-f45717e985260e9416dbd2fe8df471d48705c86a.zip external_llvm-f45717e985260e9416dbd2fe8df471d48705c86a.tar.gz external_llvm-f45717e985260e9416dbd2fe8df471d48705c86a.tar.bz2 | |
MFTB on PPC64 should really be encoded using MFSPR.
The MFTB instruction itself is being phased out, and its functionality
is provided by MFSPR. According to the ISA docs, using MFSPR works on all known
chips except for the 601 (which did not have a timebase register anyway)
and the POWER3.
Thanks to Adhemerval Zanella for pointing this out!
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@161346 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/ppc64-cyclecounter.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/ppc64-cyclecounter.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/CodeGen/PowerPC/ppc64-cyclecounter.ll b/test/CodeGen/PowerPC/ppc64-cyclecounter.ll index c1df3c7..38406ca 100644 --- a/test/CodeGen/PowerPC/ppc64-cyclecounter.ll +++ b/test/CodeGen/PowerPC/ppc64-cyclecounter.ll @@ -9,7 +9,7 @@ entry: } ; CHECK: @test1 -; CHECK: mftb +; CHECK: mfspr 3, 268 declare i64 @llvm.readcyclecounter() |