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author | Stephen Hines <srhines@google.com> | 2015-03-23 12:10:34 -0700 |
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committer | Stephen Hines <srhines@google.com> | 2015-03-23 12:10:34 -0700 |
commit | ebe69fe11e48d322045d5949c83283927a0d790b (patch) | |
tree | c92f1907a6b8006628a4b01615f38264d29834ea /test/CodeGen/PowerPC/ppc64-fastcc-fast-isel.ll | |
parent | b7d2e72b02a4cb8034f32f8247a2558d2434e121 (diff) | |
download | external_llvm-ebe69fe11e48d322045d5949c83283927a0d790b.zip external_llvm-ebe69fe11e48d322045d5949c83283927a0d790b.tar.gz external_llvm-ebe69fe11e48d322045d5949c83283927a0d790b.tar.bz2 |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
Diffstat (limited to 'test/CodeGen/PowerPC/ppc64-fastcc-fast-isel.ll')
-rw-r--r-- | test/CodeGen/PowerPC/ppc64-fastcc-fast-isel.ll | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/ppc64-fastcc-fast-isel.ll b/test/CodeGen/PowerPC/ppc64-fastcc-fast-isel.ll new file mode 100644 index 0000000..941513f --- /dev/null +++ b/test/CodeGen/PowerPC/ppc64-fastcc-fast-isel.ll @@ -0,0 +1,56 @@ +; RUN: llc -mcpu=pwr7 -mattr=-vsx -fast-isel -fast-isel-abort < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define fastcc i64 @g1(i64 %g1, double %f1, i64 %g2, double %f2, i64 %g3, double %f3, i64 %g4, double %f4) #0 { + ret i64 %g1 + +; CHECK-LABEL: @g1 +; CHECK-NOT: mr 3, +; CHECK: blr +} + +define fastcc i64 @g2(i64 %g1, double %f1, i64 %g2, double %f2, i64 %g3, double %f3, i64 %g4, double %f4) #0 { + ret i64 %g2 + +; CHECK-LABEL: @g2 +; CHECK: mr 3, 4 +; CHECK-NEXT: blr +} + +define fastcc i64 @g3(i64 %g1, double %f1, i64 %g2, double %f2, i64 %g3, double %f3, i64 %g4, double %f4) #0 { + ret i64 %g3 + +; CHECK-LABEL: @g3 +; CHECK: mr 3, 5 +; CHECK-NEXT: blr +} + +define fastcc double @f2(i64 %g1, double %f1, i64 %g2, double %f2, i64 %g3, double %f3, i64 %g4, double %f4) #0 { + ret double %f2 + +; CHECK-LABEL: @f2 +; CHECK: fmr 1, 2 +; CHECK-NEXT: blr +} + +define void @cg2(i64 %v) #0 { + tail call fastcc i64 @g1(i64 0, double 0.0, i64 %v, double 0.0, i64 0, double 0.0, i64 0, double 0.0) + ret void + +; CHECK-LABEL: @cg2 +; CHECK: mr 4, 3 +; CHECK: blr +} + +define void @cf2(double %v) #0 { + tail call fastcc i64 @g1(i64 0, double 0.0, i64 0, double %v, i64 0, double 0.0, i64 0, double 0.0) + ret void + +; CHECK-LABEL: @cf2 +; CHECK: mr 2, 1 +; CHECK: blr +} + +attributes #0 = { nounwind } + |