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| author | Stephen Hines <srhines@google.com> | 2014-05-29 02:49:00 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-05-29 02:49:00 -0700 |
| commit | dce4a407a24b04eebc6a376f8e62b41aaa7b071f (patch) | |
| tree | dcebc53f2b182f145a2e659393bf9a0472cedf23 /test/CodeGen/PowerPC/rlwimi-dyn-and.ll | |
| parent | 220b921aed042f9e520c26cffd8282a94c66c3d5 (diff) | |
| download | external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.zip external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.tar.gz external_llvm-dce4a407a24b04eebc6a376f8e62b41aaa7b071f.tar.bz2 | |
Update LLVM for 3.5 rebase (r209712).
Change-Id: I149556c940fb7dc92d075273c87ff584f400941f
Diffstat (limited to 'test/CodeGen/PowerPC/rlwimi-dyn-and.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/rlwimi-dyn-and.ll | 48 |
1 files changed, 48 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/rlwimi-dyn-and.ll b/test/CodeGen/PowerPC/rlwimi-dyn-and.ll new file mode 100644 index 0000000..e02801f --- /dev/null +++ b/test/CodeGen/PowerPC/rlwimi-dyn-and.ll @@ -0,0 +1,48 @@ +; RUN: llc -mcpu=pwr7 < %s | FileCheck %s +target datalayout = "E-m:e-i64:64-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define i32 @test1() #0 { +entry: + %conv67.reload = load i32* undef + %const = bitcast i32 65535 to i32 + br label %next + +next: + %shl161 = shl nuw nsw i32 %conv67.reload, 15 + %0 = load i8* undef, align 1 + %conv169 = zext i8 %0 to i32 + %shl170 = shl nuw nsw i32 %conv169, 7 + %const_mat = add i32 %const, -32767 + %shl161.masked = and i32 %shl161, %const_mat + %conv174 = or i32 %shl170, %shl161.masked + ret i32 %conv174 + +; CHECK-LABEL: @test1 +; CHECK-NOT: rlwimi 3, {{[0-9]+}}, 15, 0, 16 +; CHECK: blr +} + +define i32 @test2() #0 { +entry: + %conv67.reload = load i32* undef + %const = bitcast i32 65535 to i32 + br label %next + +next: + %shl161 = shl nuw nsw i32 %conv67.reload, 15 + %0 = load i8* undef, align 1 + %conv169 = zext i8 %0 to i32 + %shl170 = shl nuw nsw i32 %conv169, 7 + %shl161.masked = and i32 %shl161, 32768 + %conv174 = or i32 %shl170, %shl161.masked + ret i32 %conv174 + +; CHECK-LABEL: @test2 +; CHECK: slwi 3, {{[0-9]+}}, 7 +; CHECK: rlwimi 3, {{[0-9]+}}, 15, 16, 16 +; CHECK: blr +} + +attributes #0 = { nounwind } + |