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authorBill Wendling <isanbard@gmail.com>2008-12-12 00:56:36 +0000
committerBill Wendling <isanbard@gmail.com>2008-12-12 00:56:36 +0000
commitab55ebda1c2254f98b06e770bc2dae7d05a4a366 (patch)
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Redo the arithmetic with overflow architecture. I was changing the semantics of
ISD::ADD to emit an implicit EFLAGS. This was horribly broken. Instead, replace the intrinsic with an ISD::SADDO node. Then custom lower that into an X86ISD::ADD node with a associated SETCC that checks the correct condition code (overflow or carry). Then that gets lowered into the correct X86::ADDOvf instruction. Similar for SUB and MUL instructions. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@60915 91177308-0d34-0410-b5e6-96231b3b80d8
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