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| author | Stephen Hines <srhines@google.com> | 2015-03-23 12:10:34 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2015-03-23 12:10:34 -0700 |
| commit | ebe69fe11e48d322045d5949c83283927a0d790b (patch) | |
| tree | c92f1907a6b8006628a4b01615f38264d29834ea /test/CodeGen/PowerPC/tls-pic.ll | |
| parent | b7d2e72b02a4cb8034f32f8247a2558d2434e121 (diff) | |
| download | external_llvm-ebe69fe11e48d322045d5949c83283927a0d790b.zip external_llvm-ebe69fe11e48d322045d5949c83283927a0d790b.tar.gz external_llvm-ebe69fe11e48d322045d5949c83283927a0d790b.tar.bz2 | |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
Diffstat (limited to 'test/CodeGen/PowerPC/tls-pic.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/tls-pic.ll | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/test/CodeGen/PowerPC/tls-pic.ll b/test/CodeGen/PowerPC/tls-pic.ll index 9ba3725..6c671b0 100644 --- a/test/CodeGen/PowerPC/tls-pic.ll +++ b/test/CodeGen/PowerPC/tls-pic.ll @@ -19,32 +19,32 @@ entry: ; OPT0-LABEL: main: ; OPT0: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha -; OPT0-NEXT: addi 3, [[REG]], a@got@tlsld@l +; OPT0: addi 3, [[REG]], a@got@tlsld@l ; OPT0: bl __tls_get_addr(a@tlsld) ; OPT0-NEXT: nop ; OPT0: addis [[REG2:[0-9]+]], 3, a@dtprel@ha -; OPT0-NEXT: addi {{[0-9]+}}, [[REG2]], a@dtprel@l +; OPT0: addi {{[0-9]+}}, [[REG2]], a@dtprel@l ; OPT0-32-LABEL: main ; OPT0-32: addi {{[0-9]+}}, {{[0-9]+}}, a@got@tlsld ; OPT0-32: bl __tls_get_addr(a@tlsld)@PLT ; OPT0-32: addis [[REG:[0-9]+]], 3, a@dtprel@ha -; OPT0-32-NEXT: addi {{[0-9]+}}, [[REG]], a@dtprel@l +; OPT0-32: addi {{[0-9]+}}, [[REG]], a@dtprel@l ; OPT1-32-LABEL: main ; OPT1-32: addi 3, {{[0-9]+}}, a@got@tlsld ; OPT1-32: bl __tls_get_addr(a@tlsld)@PLT ; OPT1-32: addis [[REG:[0-9]+]], 3, a@dtprel@ha -; OPT1-32-NEXT: addi {{[0-9]+}}, [[REG]], a@dtprel@l +; OPT1-32: addi {{[0-9]+}}, [[REG]], a@dtprel@l ; Test peephole optimization for thread-local storage using the ; local dynamic model. ; OPT1-LABEL: main: ; OPT1: addis [[REG:[0-9]+]], 2, a@got@tlsld@ha -; OPT1-NEXT: addi 3, [[REG]], a@got@tlsld@l +; OPT1: addi 3, [[REG]], a@got@tlsld@l ; OPT1: bl __tls_get_addr(a@tlsld) ; OPT1-NEXT: nop ; OPT1: addis [[REG2:[0-9]+]], 3, a@dtprel@ha -; OPT1-NEXT: lwa {{[0-9]+}}, a@dtprel@l([[REG2]]) +; OPT1: lwa {{[0-9]+}}, a@dtprel@l([[REG2]]) ; Test correct assembly code generation for thread-local storage using ; the general dynamic model. @@ -60,8 +60,8 @@ entry: } ; OPT1-LABEL: main2 -; OPT1: addis [[REG:[0-9]+]], 2, a2@got@tlsgd@ha -; OPT1-NEXT: addi 3, [[REG]], a2@got@tlsgd@l +; OPT1: addis [[REG:[0-9]+]], 2, a2@got@tlsgd@ha +; OPT1: addi 3, [[REG]], a2@got@tlsgd@l ; OPT1: bl __tls_get_addr(a2@tlsgd) ; OPT1-NEXT: nop ; OPT1-32-LABEL: main2 |