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| author | Stephen Hines <srhines@google.com> | 2014-04-23 16:57:46 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-04-24 15:53:16 -0700 |
| commit | 36b56886974eae4f9c5ebc96befd3e7bfe5de338 (patch) | |
| tree | e6cfb69fbbd937f450eeb83bfb83b9da3b01275a /test/CodeGen/PowerPC/tls.ll | |
| parent | 69a8640022b04415ae9fac62f8ab090601d8f889 (diff) | |
| download | external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.zip external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.tar.gz external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.tar.bz2 | |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
Diffstat (limited to 'test/CodeGen/PowerPC/tls.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/tls.ll | 33 |
1 files changed, 29 insertions, 4 deletions
diff --git a/test/CodeGen/PowerPC/tls.ll b/test/CodeGen/PowerPC/tls.ll index 4e0a822..59b4de7 100644 --- a/test/CodeGen/PowerPC/tls.ll +++ b/test/CodeGen/PowerPC/tls.ll @@ -1,7 +1,8 @@ -target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64" -target triple = "powerpc64-unknown-freebsd10.0" -; RUN: llc -O0 < %s -march=ppc64 | FileCheck -check-prefix=OPT0 %s -; RUN: llc -O1 < %s -march=ppc64 | FileCheck -check-prefix=OPT1 %s +; RUN: llc -O0 < %s -march=ppc64 -mcpu=ppc64 | FileCheck -check-prefix=OPT0 %s +; RUN: llc -O1 < %s -march=ppc64 -mcpu=ppc64 | FileCheck -check-prefix=OPT1 %s +; RUN: llc -O0 < %s -march=ppc32 -mcpu=ppc | FileCheck -check-prefix=OPT0-PPC32 %s + +target triple = "powerpc64-unknown-linux-gnu" @a = thread_local global i32 0, align 4 @@ -19,3 +20,27 @@ entry: store i32 42, i32* @a, align 4 ret i32 0 } + +; Test correct assembly code generation for thread-local storage +; using the initial-exec model. + +@a2 = external thread_local global i32 + +define signext i32 @main2() nounwind { +entry: + %retval = alloca i32, align 4 + store i32 0, i32* %retval + %0 = load i32* @a2, align 4 + ret i32 %0 +} + +; OPT1-LABEL: main2: +; OPT1: addis [[REG1:[0-9]+]], 2, a2@got@tprel@ha +; OPT1: ld [[REG2:[0-9]+]], a2@got@tprel@l([[REG1]]) +; OPT1: add {{[0-9]+}}, [[REG2]], a2@tls + +;OPT0-PPC32-LABEL: main2: +;OPT0-PPC32: li [[REG1:[0-9]+]], _GLOBAL_OFFSET_TABLE_@l +;OPT0-PPC32: addis [[REG1]], [[REG1]], _GLOBAL_OFFSET_TABLE_@ha +;OPT0-PPC32: lwz [[REG2:[0-9]+]], a2@got@tprel@l([[REG1]]) +;OPT0-PPC32: add 3, [[REG2]], a2@tls |