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| author | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-10 22:08:18 +0000 |
|---|---|---|
| committer | Android Git Automerger <android-git-automerger@android.com> | 2015-04-10 22:08:18 +0000 |
| commit | 13a7db5b9c4f5e543d037be68ec3428216bfd550 (patch) | |
| tree | 1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/CodeGen/PowerPC/unal-altivec-wint.ll | |
| parent | 0eb46f5d1e06a4284663d636a74b06adc3a161d7 (diff) | |
| parent | 31195f0bdca6ee2a5e72d07edf13e1d81206d949 (diff) | |
| download | external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.zip external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.gz external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.bz2 | |
am 31195f0b: Merge "Update aosp/master llvm for rebase to r233350"
* commit '31195f0bdca6ee2a5e72d07edf13e1d81206d949':
Update aosp/master llvm for rebase to r233350
Diffstat (limited to 'test/CodeGen/PowerPC/unal-altivec-wint.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/unal-altivec-wint.ll | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/test/CodeGen/PowerPC/unal-altivec-wint.ll b/test/CodeGen/PowerPC/unal-altivec-wint.ll index 7e0963f..b71a98b 100644 --- a/test/CodeGen/PowerPC/unal-altivec-wint.ll +++ b/test/CodeGen/PowerPC/unal-altivec-wint.ll @@ -6,11 +6,11 @@ declare <4 x i32> @llvm.ppc.altivec.lvx(i8*) #1 define <4 x i32> @test1(<4 x i32>* %h) #0 { entry: - %h1 = getelementptr <4 x i32>* %h, i64 1 + %h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1 %hv = bitcast <4 x i32>* %h1 to i8* %vl = call <4 x i32> @llvm.ppc.altivec.lvx(i8* %hv) - %v0 = load <4 x i32>* %h, align 8 + %v0 = load <4 x i32>, <4 x i32>* %h, align 8 %a = add <4 x i32> %v0, %vl ret <4 x i32> %a @@ -27,11 +27,11 @@ declare void @llvm.ppc.altivec.stvx(<4 x i32>, i8*) #0 define <4 x i32> @test2(<4 x i32>* %h, <4 x i32> %d) #0 { entry: - %h1 = getelementptr <4 x i32>* %h, i64 1 + %h1 = getelementptr <4 x i32>, <4 x i32>* %h, i64 1 %hv = bitcast <4 x i32>* %h1 to i8* call void @llvm.ppc.altivec.stvx(<4 x i32> %d, i8* %hv) - %v0 = load <4 x i32>* %h, align 8 + %v0 = load <4 x i32>, <4 x i32>* %h, align 8 ret <4 x i32> %v0 |