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| author | Stephen Hines <srhines@google.com> | 2014-12-01 14:51:49 -0800 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-12-02 16:08:10 -0800 |
| commit | 37ed9c199ca639565f6ce88105f9e39e898d82d0 (patch) | |
| tree | 8fb36d3910e3ee4c4e1b7422f4f017108efc52f5 /test/CodeGen/PowerPC/vec-abi-align.ll | |
| parent | d2327b22152ced7bc46dc629fc908959e8a52d03 (diff) | |
| download | external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.zip external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.gz external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.bz2 | |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
Diffstat (limited to 'test/CodeGen/PowerPC/vec-abi-align.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/vec-abi-align.ll | 21 |
1 files changed, 20 insertions, 1 deletions
diff --git a/test/CodeGen/PowerPC/vec-abi-align.ll b/test/CodeGen/PowerPC/vec-abi-align.ll index 3239cf6..5075ff2 100644 --- a/test/CodeGen/PowerPC/vec-abi-align.ll +++ b/test/CodeGen/PowerPC/vec-abi-align.ll @@ -1,4 +1,5 @@ -; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 < %s | FileCheck %s +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=-vsx < %s | FileCheck %s +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-VSX %s target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -16,6 +17,10 @@ entry: ; CHECK-LABEL: @test1 ; CHECK: stvx 2, ; CHECK: blr + +; CHECK-VSX-LABEL: @test1 +; CHECK-VSX: stxvw4x 34, +; CHECK-VSX: blr } ; Function Attrs: nounwind @@ -35,6 +40,13 @@ entry: ; CHECK: addi [[REGB:[0-9]+]], 1, 112 ; CHECK: lvx 2, [[REGB]], [[REG16]] ; CHECK: blr + +; CHECK-VSX-LABEL: @test2 +; CHECK-VSX: ld {{[0-9]+}}, 112(1) +; CHECK-VSX: li [[REG16:[0-9]+]], 16 +; CHECK-VSX: addi [[REGB:[0-9]+]], 1, 112 +; CHECK-VSX: lxvw4x {{[0-9]+}}, [[REGB]], [[REG16]] +; CHECK-VSX: blr } ; Function Attrs: nounwind @@ -54,6 +66,13 @@ entry: ; CHECK: addi [[REGB:[0-9]+]], 1, 128 ; CHECK: lvx 2, [[REGB]], [[REG16]] ; CHECK: blr + +; CHECK-VSX-LABEL: @test3 +; CHECK-VSX: ld {{[0-9]+}}, 128(1) +; CHECK-VSX: li [[REG16:[0-9]+]], 16 +; CHECK-VSX: addi [[REGB:[0-9]+]], 1, 128 +; CHECK-VSX: lxvw4x {{[0-9]+}}, [[REGB]], [[REG16]] +; CHECK-VSX: blr } attributes #0 = { nounwind } |