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| author | Benjamin Kramer <benny.kra@googlemail.com> | 2013-01-12 19:06:44 +0000 |
|---|---|---|
| committer | Benjamin Kramer <benny.kra@googlemail.com> | 2013-01-12 19:06:44 +0000 |
| commit | 4dc478308f0de13d9ce20915193ac8c3318c5bd6 (patch) | |
| tree | 9d13732c71847fea363a48ddd2852feb64875da8 /test/CodeGen/PowerPC/vec_extload.ll | |
| parent | edaf85606d7ac8368dd7fa0e9fd4042e523a6e3a (diff) | |
| download | external_llvm-4dc478308f0de13d9ce20915193ac8c3318c5bd6.zip external_llvm-4dc478308f0de13d9ce20915193ac8c3318c5bd6.tar.gz external_llvm-4dc478308f0de13d9ce20915193ac8c3318c5bd6.tar.bz2 | |
When lowering an inreg sext first shift left, then right arithmetically.
Shifting right two times will only yield zero. Should fix
SingleSource/UnitTests/SignlessTypes/factor.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172322 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC/vec_extload.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/vec_extload.ll | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/test/CodeGen/PowerPC/vec_extload.ll b/test/CodeGen/PowerPC/vec_extload.ll index 42334d7..998645d 100644 --- a/test/CodeGen/PowerPC/vec_extload.ll +++ b/test/CodeGen/PowerPC/vec_extload.ll @@ -15,7 +15,7 @@ define <16 x i8> @v16si8_sext_in_reg(<16 x i8> %a) { ret <16 x i8> %c } ; CHECK: v16si8_sext_in_reg: -; CHECK: vsrb +; CHECK: vslb ; CHECK: vsrab ; CHECK: blr @@ -37,7 +37,7 @@ define <8 x i16> @v8si16_sext_in_reg(<8 x i16> %a) { ret <8 x i16> %c } ; CHECK: v8si16_sext_in_reg: -; CHECK: vsrh +; CHECK: vslh ; CHECK: vsrah ; CHECK: blr @@ -61,7 +61,7 @@ define <4 x i32> @v4si32_sext_in_reg(<4 x i32> %a) { ret <4 x i32> %c } ; CHECK: v4si32_sext_in_reg: -; CHECK: vsrw +; CHECK: vslw ; CHECK: vsraw ; CHECK: blr |