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| author | Pirama Arumuga Nainar <pirama@google.com> | 2015-04-10 22:08:18 +0000 |
|---|---|---|
| committer | Android Git Automerger <android-git-automerger@android.com> | 2015-04-10 22:08:18 +0000 |
| commit | 13a7db5b9c4f5e543d037be68ec3428216bfd550 (patch) | |
| tree | 1b2c9792582e12f5af0b1512e3094425f0dc0df9 /test/CodeGen/PowerPC/vec_mul_even_odd.ll | |
| parent | 0eb46f5d1e06a4284663d636a74b06adc3a161d7 (diff) | |
| parent | 31195f0bdca6ee2a5e72d07edf13e1d81206d949 (diff) | |
| download | external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.zip external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.gz external_llvm-13a7db5b9c4f5e543d037be68ec3428216bfd550.tar.bz2 | |
am 31195f0b: Merge "Update aosp/master llvm for rebase to r233350"
* commit '31195f0bdca6ee2a5e72d07edf13e1d81206d949':
Update aosp/master llvm for rebase to r233350
Diffstat (limited to 'test/CodeGen/PowerPC/vec_mul_even_odd.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/vec_mul_even_odd.ll | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/vec_mul_even_odd.ll b/test/CodeGen/PowerPC/vec_mul_even_odd.ll new file mode 100644 index 0000000..b24bafd --- /dev/null +++ b/test/CodeGen/PowerPC/vec_mul_even_odd.ll @@ -0,0 +1,42 @@ +; Check the vector multiply even/odd word instructions that were added in P8 +; +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s +; RUN: llc -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s + +declare <2 x i64> @llvm.ppc.altivec.vmuleuw(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i64> @llvm.ppc.altivec.vmulesw(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i64> @llvm.ppc.altivec.vmulouw(<4 x i32>, <4 x i32>) nounwind readnone +declare <2 x i64> @llvm.ppc.altivec.vmulosw(<4 x i32>, <4 x i32>) nounwind readnone +declare <4 x i32> @llvm.ppc.altivec.vmuluwm(<4 x i32>, <4 x i32>) nounwind readnone + +define <2 x i64> @test_vmuleuw(<4 x i32> %x, <4 x i32> %y) nounwind readnone { + %tmp = tail call <2 x i64> @llvm.ppc.altivec.vmuleuw(<4 x i32> %x, <4 x i32> %y) + ret <2 x i64> %tmp +; CHECK: vmuleuw 2, 2, 3 +} + +define <2 x i64> @test_vmulesw(<4 x i32> %x, <4 x i32> %y) nounwind readnone { + %tmp = tail call <2 x i64> @llvm.ppc.altivec.vmulesw(<4 x i32> %x, <4 x i32> %y) + ret <2 x i64> %tmp +; CHECK: vmulesw 2, 2, 3 +} + +define <2 x i64> @test_vmulouw(<4 x i32> %x, <4 x i32> %y) nounwind readnone { + %tmp = tail call <2 x i64> @llvm.ppc.altivec.vmulouw(<4 x i32> %x, <4 x i32> %y) + ret <2 x i64> %tmp +; CHECK: vmulouw 2, 2, 3 +} + +define <2 x i64> @test_vmulosw(<4 x i32> %x, <4 x i32> %y) nounwind readnone { + %tmp = tail call <2 x i64> @llvm.ppc.altivec.vmulosw(<4 x i32> %x, <4 x i32> %y) + ret <2 x i64> %tmp +; CHECK: vmulosw 2, 2, 3 +} + +define <4 x i32> @test_vmuluwm(<4 x i32> %x, <4 x i32> %y) nounwind readnone { + %tmp = mul <4 x i32> %x, %y + ret <4 x i32> %tmp +; CHECK-LABEL: test_vmuluwm +; CHECK: vmuluwm 2, 2, 3 +} + |