diff options
| author | Stephen Hines <srhines@google.com> | 2014-12-01 14:51:49 -0800 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-12-02 16:08:10 -0800 |
| commit | 37ed9c199ca639565f6ce88105f9e39e898d82d0 (patch) | |
| tree | 8fb36d3910e3ee4c4e1b7422f4f017108efc52f5 /test/CodeGen/PowerPC/vsx-fma-m.ll | |
| parent | d2327b22152ced7bc46dc629fc908959e8a52d03 (diff) | |
| download | external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.zip external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.gz external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.bz2 | |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
Diffstat (limited to 'test/CodeGen/PowerPC/vsx-fma-m.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/vsx-fma-m.ll | 14 |
1 files changed, 10 insertions, 4 deletions
diff --git a/test/CodeGen/PowerPC/vsx-fma-m.ll b/test/CodeGen/PowerPC/vsx-fma-m.ll index da4a204..9dff9a7 100644 --- a/test/CodeGen/PowerPC/vsx-fma-m.ll +++ b/test/CodeGen/PowerPC/vsx-fma-m.ll @@ -177,21 +177,27 @@ entry: store <2 x double> %1, <2 x double>* %arrayidx3, align 8 ret void +; Note: There is some unavoidable changeability in this variant. If the +; FMAs are reordered differently, the algorithm can pick a different +; multiplicand to destroy, changing the register assignment. There isn't +; a good way to express this possibility, so hopefully this doesn't change +; too often. + ; CHECK-LABEL: @testv3 ; CHECK-DAG: xxlor [[V1:[0-9]+]], 34, 34 -; CHECK-DAG: xvmaddmdp 37, 35, 34 ; CHECK-DAG: li [[C1:[0-9]+]], 48 ; CHECK-DAG: li [[C2:[0-9]+]], 32 -; CHECK-DAG: xvmaddadp 34, 35, 38 +; CHECK-DAG: xvmaddmdp 37, 35, 34 ; CHECK-DAG: li [[C3:[0-9]+]], 16 ; Note: We could convert this next FMA to M-type as well, but it would require ; re-ordering the instructions. ; CHECK-DAG: xvmaddadp [[V1]], 35, 36 -; CHECK-DAG: xvmaddmdp 35, 36, 37 +; CHECK-DAG: xvmaddmdp 36, 35, 37 +; CHECK-DAG: xvmaddadp 34, 35, 38 ; CHECK-DAG: stxvd2x 32, 0, 3 -; CHECK-DAG: stxvd2x 35, 3, [[C1]] +; CHECK-DAG: stxvd2x 36, 3, [[C1]] ; CHECK-DAG: stxvd2x 34, 3, [[C2]] ; CHECK-DAG: stxvd2x 37, 3, [[C3]] ; CHECK: blr |