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| author | Stephen Hines <srhines@google.com> | 2015-03-23 12:10:34 -0700 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2015-03-23 12:10:34 -0700 |
| commit | ebe69fe11e48d322045d5949c83283927a0d790b (patch) | |
| tree | c92f1907a6b8006628a4b01615f38264d29834ea /test/CodeGen/PowerPC/vsx-p8.ll | |
| parent | b7d2e72b02a4cb8034f32f8247a2558d2434e121 (diff) | |
| download | external_llvm-ebe69fe11e48d322045d5949c83283927a0d790b.zip external_llvm-ebe69fe11e48d322045d5949c83283927a0d790b.tar.gz external_llvm-ebe69fe11e48d322045d5949c83283927a0d790b.tar.bz2 | |
Update aosp/master LLVM for rebase to r230699.
Change-Id: I2b5be30509658cb8266be782de0ab24f9099f9b9
Diffstat (limited to 'test/CodeGen/PowerPC/vsx-p8.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/vsx-p8.ll | 25 |
1 files changed, 19 insertions, 6 deletions
diff --git a/test/CodeGen/PowerPC/vsx-p8.ll b/test/CodeGen/PowerPC/vsx-p8.ll index 81406b6..d5a1905 100644 --- a/test/CodeGen/PowerPC/vsx-p8.ll +++ b/test/CodeGen/PowerPC/vsx-p8.ll @@ -1,4 +1,7 @@ ; RUN: llc -mcpu=pwr8 -mattr=+power8-vector < %s | FileCheck %s +; RUN: llc -mcpu=pwr8 -mattr=+power8-vector < %s | FileCheck -check-prefix=CHECK-REG %s +; RUN: llc -mcpu=pwr8 -mattr=+power8-vector -fast-isel -O0 < %s | FileCheck %s +; RUN: llc -mcpu=pwr8 -mattr=+power8-vector -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -26,17 +29,27 @@ define <4 x float> @test32u(<4 x float>* %a) { %v = load <4 x float>* %a, align 8 ret <4 x float> %v -; CHECK-LABEL: @test32u -; CHECK: lxvw4x 34, 0, 3 -; CHECK: blr +; CHECK-REG-LABEL: @test32u +; CHECK-REG: lxvw4x 34, 0, 3 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test32u +; CHECK-FISL: lxvw4x 0, 0, 3 +; CHECK-FISL: xxlor 34, 0, 0 +; CHECK-FISL: blr } define void @test33u(<4 x float>* %a, <4 x float> %b) { store <4 x float> %b, <4 x float>* %a, align 8 ret void -; CHECK-LABEL: @test33u -; CHECK: stxvw4x 34, 0, 3 -; CHECK: blr +; CHECK-REG-LABEL: @test33u +; CHECK-REG: stxvw4x 34, 0, 3 +; CHECK-REG: blr + +; CHECK-FISL-LABEL: @test33u +; CHECK-FISL: vor 3, 2, 2 +; CHECK-FISL: stxvw4x 35, 0, 3 +; CHECK-FISL: blr } |