diff options
| author | Stephen Hines <srhines@google.com> | 2015-04-01 18:49:24 +0000 |
|---|---|---|
| committer | Gerrit Code Review <noreply-gerritcodereview@google.com> | 2015-04-01 18:49:26 +0000 |
| commit | 3fa16bd6062e23bcdb82ed4dd965674792e6b761 (patch) | |
| tree | 9348fc507292f7e8715d22d64ce5a32131b4f875 /test/CodeGen/PowerPC/vsx-spill.ll | |
| parent | beed47390a60f6f0c77532b3d3f76bb47ef49423 (diff) | |
| parent | ebe69fe11e48d322045d5949c83283927a0d790b (diff) | |
| download | external_llvm-3fa16bd6062e23bcdb82ed4dd965674792e6b761.zip external_llvm-3fa16bd6062e23bcdb82ed4dd965674792e6b761.tar.gz external_llvm-3fa16bd6062e23bcdb82ed4dd965674792e6b761.tar.bz2 | |
Merge "Update aosp/master LLVM for rebase to r230699."
Diffstat (limited to 'test/CodeGen/PowerPC/vsx-spill.ll')
| -rw-r--r-- | test/CodeGen/PowerPC/vsx-spill.ll | 31 |
1 files changed, 23 insertions, 8 deletions
diff --git a/test/CodeGen/PowerPC/vsx-spill.ll b/test/CodeGen/PowerPC/vsx-spill.ll index 29bc6fc..032bcf6 100644 --- a/test/CodeGen/PowerPC/vsx-spill.ll +++ b/test/CodeGen/PowerPC/vsx-spill.ll @@ -1,4 +1,7 @@ ; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -mattr=+vsx < %s | FileCheck -check-prefix=CHECK-REG %s +; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | FileCheck %s +; RUN: llc -mcpu=pwr7 -mattr=+vsx -fast-isel -O0 < %s | FileCheck -check-prefix=CHECK-FISL %s target datalayout = "E-m:e-i64:64-n32:64" target triple = "powerpc64-unknown-linux-gnu" @@ -7,10 +10,16 @@ entry: call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind br label %return -; CHECK: @foo1 -; CHECK: xxlor [[R1:[0-9]+]], 1, 1 -; CHECK: xxlor 1, [[R1]], [[R1]] -; CHECK: blr +; CHECK-REG: @foo1 +; CHECK-REG: xxlor [[R1:[0-9]+]], 1, 1 +; CHECK-REG: xxlor 1, [[R1]], [[R1]] +; CHECK-REG: blr + +; CHECK-FISL: @foo1 +; CHECK-FISL: lis 0, -1 +; CHECK-FISL: ori 0, 0, 65384 +; CHECK-FISL: stxsdx 1, 1, 0 +; CHECK-FISL: blr return: ; preds = %entry ret double %a @@ -22,10 +31,16 @@ entry: call void asm sideeffect "", "~{f0},~{f1},~{f2},~{f3},~{f4},~{f5},~{f6},~{f7},~{f8},~{f9},~{f10},~{f11},~{f12},~{f13},~{f14},~{f15},~{f16},~{f17},~{f18},~{f19},~{f20},~{f21},~{f22},~{f23},~{f24},~{f25},~{f26},~{f27},~{f28},~{f29},~{f30},~{f31}"() nounwind br label %return -; CHECK: @foo2 -; CHECK: {{xxlor|xsadddp}} [[R1:[0-9]+]], 1, 1 -; CHECK: {{xxlor|xsadddp}} 1, [[R1]], [[R1]] -; CHECK: blr +; CHECK-REG: @foo2 +; CHECK-REG: {{xxlor|xsadddp}} [[R1:[0-9]+]], 1, 1 +; CHECK-REG: {{xxlor|xsadddp}} 1, [[R1]], [[R1]] +; CHECK-REG: blr + +; CHECK-FISL: @foo2 +; CHECK-FISL: xsadddp [[R1:[0-9]+]], 1, 1 +; CHECK-FISL: stxsdx [[R1]], [[R1]], 0 +; CHECK-FISL: lxsdx [[R1]], [[R1]], 0 +; CHECK-FISL: blr return: ; preds = %entry ret double %b |