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| author | Hal Finkel <hfinkel@anl.gov> | 2013-03-15 05:06:04 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-03-15 05:06:04 +0000 |
| commit | 0cfb42adb5072fb19a01dba3ea58a33fd5927947 (patch) | |
| tree | 10dabd9db4af644892adfbb84017e89c87c5308c /test/CodeGen/PowerPC | |
| parent | c6aa8348363c67d6ef1fac87e1d933742bf41403 (diff) | |
| download | external_llvm-0cfb42adb5072fb19a01dba3ea58a33fd5927947.zip external_llvm-0cfb42adb5072fb19a01dba3ea58a33fd5927947.tar.gz external_llvm-0cfb42adb5072fb19a01dba3ea58a33fd5927947.tar.bz2 | |
Allocate the RS spill slot for any PPC function with spills and a large stack frame
For spills into a large stack frame, the FI-elimination code uses the register
scavenger to obtain a free GPR for use with an r+r-addressed load or store.
When there are no available GPRs, the scavenger gets one by using its spill
slot. Previously, we were not always allocating that spill slot and the RS
would assert when the spill slot was needed.
I don't currently have a small test that triggered the assert, but I've
created a small regression test that verifies that the spill slot is now
added when the stack frame is sufficiently large.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177140 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC')
| -rw-r--r-- | test/CodeGen/PowerPC/2010-02-12-saveCR.ll | 6 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/frame-size.ll | 32 |
2 files changed, 35 insertions, 3 deletions
diff --git a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll index 433fe5c..0da6e43 100644 --- a/test/CodeGen/PowerPC/2010-02-12-saveCR.ll +++ b/test/CodeGen/PowerPC/2010-02-12-saveCR.ll @@ -9,12 +9,12 @@ entry: ;CHECK: mfcr r0 ;CHECK: lis r2, 1 ;CHECK: rlwinm r0, r0, 8, 0, 31 -;CHECK: ori r2, r2, 34524 +;CHECK: ori r2, r2, 34540 ;CHECK: stwx r0, r1, r2 ; Make sure that the register scavenger returns the same temporary register. ;CHECK: lis r2, 1 ;CHECK: mfcr r0 -;CHECK: ori r2, r2, 34520 +;CHECK: ori r2, r2, 34536 ;CHECK: rlwinm r0, r0, 12, 0, 31 ;CHECK: stwx r0, r1, r2 %x = alloca [100000 x i8] ; <[100000 x i8]*> [#uses=1] @@ -26,7 +26,7 @@ entry: return: ; preds = %entry ;CHECK: lis r2, 1 -;CHECK: ori r2, r2, 34524 +;CHECK: ori r2, r2, 34540 ;CHECK: lwzx r0, r1, r2 ;CHECK: rlwinm r0, r0, 24, 0, 31 ;CHECK: mtcrf 32, r0 diff --git a/test/CodeGen/PowerPC/frame-size.ll b/test/CodeGen/PowerPC/frame-size.ll new file mode 100644 index 0000000..0e569a4 --- /dev/null +++ b/test/CodeGen/PowerPC/frame-size.ll @@ -0,0 +1,32 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=a2 | FileCheck %s +target datalayout = "E-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f128:64:128-n32" + +define i64 @foo() nounwind { +entry: + %x = alloca [32568 x i8] + %"alloca point" = bitcast i32 0 to i32 + %x1 = bitcast [32568 x i8]* %x to i8* + +; Check that the RS spill slot has been allocated (because the estimate +; will fail the small-frame-size check and the function has spills). +; CHECK: @foo +; CHECK: stdu 1, -32768(1) + + %s1 = call i64 @bar(i8* %x1) nounwind + %s2 = call i64 @bar(i8* %x1) nounwind + %s3 = call i64 @bar(i8* %x1) nounwind + %s4 = call i64 @bar(i8* %x1) nounwind + %s5 = call i64 @bar(i8* %x1) nounwind + %s6 = call i64 @bar(i8* %x1) nounwind + %s7 = call i64 @bar(i8* %x1) nounwind + %s8 = call i64 @bar(i8* %x1) nounwind + %r = call i64 @can(i64 %s1, i64 %s2, i64 %s3, i64 %s4, i64 %s5, i64 %s6, i64 %s7, i64 %s8) nounwind + br label %return + +return: + ret i64 %r +} + +declare i64 @bar(i8*) +declare i64 @can(i64, i64, i64, i64, i64, i64, i64, i64) + |