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| author | Hal Finkel <hfinkel@anl.gov> | 2013-03-21 19:03:21 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-03-21 19:03:21 +0000 |
| commit | 10f7f2a222d0e83dc0c33ad506a7686190c2f7a2 (patch) | |
| tree | 7a0756c7eacdb202839bfdf5c7a5b165ae758257 /test/CodeGen/PowerPC | |
| parent | e9cc0a09ae38c87b1b26a44f5e32222ede4f84e6 (diff) | |
| download | external_llvm-10f7f2a222d0e83dc0c33ad506a7686190c2f7a2.zip external_llvm-10f7f2a222d0e83dc0c33ad506a7686190c2f7a2.tar.gz external_llvm-10f7f2a222d0e83dc0c33ad506a7686190c2f7a2.tar.bz2 | |
Add support for spilling VRSAVE on PPC
Although there is only one Altivec VRSAVE register, it is a member of
a register class, and we need the ability to spill it. Because this
register is normally callee-preserved and handled by special code this
has never before been necessary. However, this capability will be required by
a forthcoming commit adding SjLj support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@177654 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC')
| -rw-r--r-- | test/CodeGen/PowerPC/vrsave-spill.ll | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/test/CodeGen/PowerPC/vrsave-spill.ll b/test/CodeGen/PowerPC/vrsave-spill.ll new file mode 100644 index 0000000..d4b07bc --- /dev/null +++ b/test/CodeGen/PowerPC/vrsave-spill.ll @@ -0,0 +1,18 @@ +; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=g5 | FileCheck %s +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +define <4 x float> @foo(<4 x float> %a, <4 x float> %b) nounwind { +entry: + %c = fadd <4 x float> %a, %b + call void asm sideeffect "", "~{VRsave}"() nounwind + br label %return + +; CHECK: @foo +; CHECK: mfspr {{[0-9]+}}, 256 +; CHECK: mtspr 256, {{[0-9]+}} + +return: ; preds = %entry + ret <4 x float> %c +} + |