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author | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2013-10-17 11:02:58 +0000 |
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committer | Andrea Di Biagio <Andrea_DiBiagio@sn.scee.net> | 2013-10-17 11:02:58 +0000 |
commit | 888cbad774acdff580611f6b07daaf96e825b7e7 (patch) | |
tree | 22f43761786a3b5d5a9d69ae13c789ae3a7d2e0d /test/CodeGen/PowerPC | |
parent | f5e3811607dd54fded0bb6b6ab97345446e086b9 (diff) | |
download | external_llvm-888cbad774acdff580611f6b07daaf96e825b7e7.zip external_llvm-888cbad774acdff580611f6b07daaf96e825b7e7.tar.gz external_llvm-888cbad774acdff580611f6b07daaf96e825b7e7.tar.bz2 |
Fix edge condition in DAGCombiner to improve codegen of shift sequences.
When canonicalizing dags according to the rule
(shl (zext (shr X, c1) ), c1) ==> (zext (shl (shr X, c1), c1))
remember to add the new shl dag to the DAGCombiner worklist of nodes.
If we don't explicitly add it to the worklist of nodes to visit, we
may not trigger later on the rule that folds the shift left + logical
shift right into a AND instruction with bitmask.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192883 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC')
0 files changed, 0 insertions, 0 deletions