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authorAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>2013-10-17 11:02:58 +0000
committerAndrea Di Biagio <Andrea_DiBiagio@sn.scee.net>2013-10-17 11:02:58 +0000
commit888cbad774acdff580611f6b07daaf96e825b7e7 (patch)
tree22f43761786a3b5d5a9d69ae13c789ae3a7d2e0d /test/CodeGen/PowerPC
parentf5e3811607dd54fded0bb6b6ab97345446e086b9 (diff)
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Fix edge condition in DAGCombiner to improve codegen of shift sequences.
When canonicalizing dags according to the rule (shl (zext (shr X, c1) ), c1) ==> (zext (shl (shr X, c1), c1)) remember to add the new shl dag to the DAGCombiner worklist of nodes. If we don't explicitly add it to the worklist of nodes to visit, we may not trigger later on the rule that folds the shift left + logical shift right into a AND instruction with bitmask. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192883 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC')
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