Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally.

This update was done with the following bash script:

  find test/CodeGen -name "*.ll" | \
  while read NAME; do
    echo "$NAME"
    if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
      TEMP=`mktemp -t temp`
      cp $NAME $TEMP
      sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
      while read FUNC; do
        sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
      done
      sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
      sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
      sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
      sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
      mv $TEMP $NAME
    fi
  done


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186280 91177308-0d34-0410-b5e6-96231b3b80d8

21 files changed, 128 insertions, 128 deletions

diff --git a/test/CodeGen/PowerPC/2009-09-18-carrybit.ll b/test/CodeGen/PowerPC/2009-09-18-carrybit.ll
index 6c23a61..8d5ea8a 100644
--- a/test/CodeGen/PowerPC/2009-09-18-carrybit.ll
+++ b/test/CodeGen/PowerPC/2009-09-18-carrybit.ll
@@ -5,7 +5,7 @@ target triple = "powerpc-apple-darwin9.6"
 
 define i64 @foo(i64 %r.0.ph, i64 %q.0.ph, i32 %sr1.1.ph) nounwind {
 entry:
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: subfc
 ; CHECK: subfe
 ; CHECK: subfc
diff --git a/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll b/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll
index d1a3c9f..a25ce07 100644
--- a/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll
+++ b/test/CodeGen/PowerPC/2010-12-18-PPCStackRefs.ll
@@ -6,7 +6,7 @@ target triple = "powerpc-apple-darwin9.8"
 define i32 @main() nounwind {
 entry:
 ; Make sure we're generating references using the red zone
-; CHECK: main:
+; CHECK-LABEL: main:
 ; CHECK: stw r2, -12(r1)
   %retval = alloca i32
   %0 = alloca i32
diff --git a/test/CodeGen/PowerPC/addc.ll b/test/CodeGen/PowerPC/addc.ll
index 8c928ce..500d126 100644
--- a/test/CodeGen/PowerPC/addc.ll
+++ b/test/CodeGen/PowerPC/addc.ll
@@ -5,7 +5,7 @@ define i64 @add_ll(i64 %a, i64 %b) nounwind {
 entry:
         %tmp.2 = add i64 %b, %a         ; <i64> [#uses=1]
         ret i64 %tmp.2
-; CHECK: add_ll:
+; CHECK-LABEL: add_ll:
 ; CHECK: addc r4, r6, r4
 ; CHECK: adde r3, r5, r3
 ; CHECK: blr
@@ -15,7 +15,7 @@ define i64 @add_l_5(i64 %a) nounwind {
 entry:
         %tmp.1 = add i64 %a, 5          ; <i64> [#uses=1]
         ret i64 %tmp.1
-; CHECK: add_l_5:
+; CHECK-LABEL: add_l_5:
 ; CHECK: addic r4, r4, 5
 ; CHECK: addze r3, r3
 ; CHECK: blr
@@ -25,7 +25,7 @@ define i64 @add_l_m5(i64 %a) nounwind {
 entry:
         %tmp.1 = add i64 %a, -5         ; <i64> [#uses=1]
         ret i64 %tmp.1
-; CHECK: add_l_m5:
+; CHECK-LABEL: add_l_m5:
 ; CHECK: addic r4, r4, -5
 ; CHECK: addme r3, r3
 ; CHECK: blr
diff --git a/test/CodeGen/PowerPC/anon_aggr.ll b/test/CodeGen/PowerPC/anon_aggr.ll
index cf39168..1525e05 100644
--- a/test/CodeGen/PowerPC/anon_aggr.ll
+++ b/test/CodeGen/PowerPC/anon_aggr.ll
@@ -20,7 +20,7 @@ unequal:
   ret i8* %ptr
 }
 
-; CHECK: func1:
+; CHECK-LABEL: func1:
 ; CHECK: cmpld {{[0-9]+}}, 4, 5
 ; CHECK-DAG: std 4, -[[OFFSET1:[0-9]+]]
 ; CHECK-DAG: std 5, -[[OFFSET2:[0-9]+]]
@@ -61,7 +61,7 @@ unequal:
   ret i8* %array2_ptr
 }
 
-; CHECK: func2:
+; CHECK-LABEL: func2:
 ; CHECK: addi [[REG1:[0-9]+]], 1, 64
 ; CHECK: ld [[REG2:[0-9]+]], 8([[REG1]])
 ; CHECK: cmpld {{[0-9]+}}, 4, [[REG2]]
@@ -107,7 +107,7 @@ unequal:
   ret i8* %array2_ptr
 }
 
-; CHECK: func3:
+; CHECK-LABEL: func3:
 ; CHECK: addi [[REG1:[0-9]+]], 1, 64
 ; CHECK: addi [[REG2:[0-9]+]], 1, 48
 ; CHECK: ld [[REG3:[0-9]+]], 8([[REG1]])
@@ -156,7 +156,7 @@ unequal:
   ret i8* %array2_ptr
 }
 
-; CHECK: func4:
+; CHECK-LABEL: func4:
 ; CHECK: addi [[REG1:[0-9]+]], 1, 128
 ; CHECK: ld [[REG2:[0-9]+]], 120(1)
 ; CHECK: ld [[REG3:[0-9]+]], 8([[REG1]])
diff --git a/test/CodeGen/PowerPC/atomic-1.ll b/test/CodeGen/PowerPC/atomic-1.ll
index 838db20..1737916 100644
--- a/test/CodeGen/PowerPC/atomic-1.ll
+++ b/test/CodeGen/PowerPC/atomic-1.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -mtriple=powerpc-apple-darwin -march=ppc32 |  FileCheck %s
 
 define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind {
-; CHECK: exchange_and_add:
+; CHECK-LABEL: exchange_and_add:
 ; CHECK: lwarx {{r[0-9]+}}, 0, {{r[0-9]+}}
   %tmp = atomicrmw add i32* %mem, i32 %val monotonic
 ; CHECK: stwcx. {{r[0-9]+}}, 0, {{r[0-9]+}}
@@ -9,7 +9,7 @@ define i32 @exchange_and_add(i32* %mem, i32 %val) nounwind {
 }
 
 define i32 @exchange_and_cmp(i32* %mem) nounwind {
-; CHECK: exchange_and_cmp:
+; CHECK-LABEL: exchange_and_cmp:
 ; CHECK: lwarx
   %tmp = cmpxchg i32* %mem, i32 0, i32 1 monotonic
 ; CHECK: stwcx.
@@ -18,7 +18,7 @@ define i32 @exchange_and_cmp(i32* %mem) nounwind {
 }
 
 define i32 @exchange(i32* %mem, i32 %val) nounwind {
-; CHECK: exchange:
+; CHECK-LABEL: exchange:
 ; CHECK: lwarx
   %tmp = atomicrmw xchg i32* %mem, i32 1 monotonic
 ; CHECK: stwcx.
diff --git a/test/CodeGen/PowerPC/atomic-2.ll b/test/CodeGen/PowerPC/atomic-2.ll
index 40b4a2e..e56a779 100644
--- a/test/CodeGen/PowerPC/atomic-2.ll
+++ b/test/CodeGen/PowerPC/atomic-2.ll
@@ -1,7 +1,7 @@
 ; RUN: llc < %s -march=ppc64 | FileCheck %s
 
 define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind {
-; CHECK: exchange_and_add:
+; CHECK-LABEL: exchange_and_add:
 ; CHECK: ldarx
   %tmp = atomicrmw add i64* %mem, i64 %val monotonic
 ; CHECK: stdcx.
@@ -9,7 +9,7 @@ define i64 @exchange_and_add(i64* %mem, i64 %val) nounwind {
 }
 
 define i64 @exchange_and_cmp(i64* %mem) nounwind {
-; CHECK: exchange_and_cmp:
+; CHECK-LABEL: exchange_and_cmp:
 ; CHECK: ldarx
   %tmp = cmpxchg i64* %mem, i64 0, i64 1 monotonic
 ; CHECK: stdcx.
@@ -18,7 +18,7 @@ define i64 @exchange_and_cmp(i64* %mem) nounwind {
 }
 
 define i64 @exchange(i64* %mem, i64 %val) nounwind {
-; CHECK: exchange:
+; CHECK-LABEL: exchange:
 ; CHECK: ldarx
   %tmp = atomicrmw xchg i64* %mem, i64 1 monotonic
 ; CHECK: stdcx.
diff --git a/test/CodeGen/PowerPC/complex-return.ll b/test/CodeGen/PowerPC/complex-return.ll
index f12152f..3eb30e9 100644
--- a/test/CodeGen/PowerPC/complex-return.ll
+++ b/test/CodeGen/PowerPC/complex-return.ll
@@ -23,7 +23,7 @@ entry:
   ret { ppc_fp128, ppc_fp128 } %0
 }
 
-; CHECK: foo:
+; CHECK-LABEL: foo:
 ; CHECK: lfd 3
 ; CHECK: lfd 4
 ; CHECK: lfd 2
@@ -49,7 +49,7 @@ entry:
   ret { float, float } %0
 }
 
-; CHECK: oof:
+; CHECK-LABEL: oof:
 ; CHECK: lfs 2
 ; CHECK: lfs 1
 
diff --git a/test/CodeGen/PowerPC/dbg.ll b/test/CodeGen/PowerPC/dbg.ll
index 21e3661..840ce98 100644
--- a/test/CodeGen/PowerPC/dbg.ll
+++ b/test/CodeGen/PowerPC/dbg.ll
@@ -1,5 +1,5 @@
 ; RUN: llc < %s -break-anti-dependencies=all -march=ppc64 -mcpu=g5 | FileCheck %s
-; CHECK: main:
+; CHECK-LABEL: main:
 
 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v128:128:128-n32:64"
 target triple = "powerpc64-unknown-linux-gnu"
diff --git a/test/CodeGen/PowerPC/emptystruct.ll b/test/CodeGen/PowerPC/emptystruct.ll
index c6dae82..47cfadd 100644
--- a/test/CodeGen/PowerPC/emptystruct.ll
+++ b/test/CodeGen/PowerPC/emptystruct.ll
@@ -25,7 +25,7 @@ entry:
   ret void
 }
 
-; CHECK: callee:
+; CHECK-LABEL: callee:
 ; CHECK: std 4,
 ; CHECK-NOT: std 5,
 ; CHECK-NOT: std 6,
@@ -42,7 +42,7 @@ entry:
   ret void
 }
 
-; CHECK: caller:
+; CHECK-LABEL: caller:
 ; CHECK: addi 4,
 ; CHECK-NOT: std 5,
 ; CHECK-NOT: std 6,
diff --git a/test/CodeGen/PowerPC/indirectbr.ll b/test/CodeGen/PowerPC/indirectbr.ll
index 4b6f88b..fd06fd9 100644
--- a/test/CodeGen/PowerPC/indirectbr.ll
+++ b/test/CodeGen/PowerPC/indirectbr.ll
@@ -6,9 +6,9 @@
 @C.0.2070 = private constant [5 x i8*] [i8* blockaddress(@foo, %L1), i8* blockaddress(@foo, %L2), i8* blockaddress(@foo, %L3), i8* blockaddress(@foo, %L4), i8* blockaddress(@foo, %L5)] ; <[5 x i8*]*> [#uses=1]
 
 define internal i32 @foo(i32 %i) nounwind {
-; PIC: foo:
-; STATIC: foo:
-; PPC64: foo:
+; PIC-LABEL: foo:
+; STATIC-LABEL: foo:
+; PPC64-LABEL: foo:
 entry:
   %0 = load i8** @nextaddr, align 4               ; <i8*> [#uses=2]
   %1 = icmp eq i8* %0, null                       ; <i1> [#uses=1]
diff --git a/test/CodeGen/PowerPC/ppc64-toc.ll b/test/CodeGen/PowerPC/ppc64-toc.ll
index 7f30ef8..f349919 100644
--- a/test/CodeGen/PowerPC/ppc64-toc.ll
+++ b/test/CodeGen/PowerPC/ppc64-toc.ll
@@ -8,7 +8,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 
 define i64 @access_int64(i64 %a) nounwind readonly {
 entry:
-; CHECK: access_int64:
+; CHECK-LABEL: access_int64:
 ; CHECK-NEXT: .align  3
 ; CHECK-NEXT: .quad   .L.access_int64
 ; CHECK-NEXT: .quad   .TOC.@tocbase
@@ -23,7 +23,7 @@ entry:
 
 define i64 @internal_static_var(i64 %a) nounwind {
 entry:
-; CHECK: internal_static_var:
+; CHECK-LABEL: internal_static_var:
 ; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
   %0 = load i64* @internal_static_var.x, align 8
   %cmp = icmp eq i64 %0, %a
@@ -33,7 +33,7 @@ entry:
 
 define i32 @access_double(double %a) nounwind readnone {
 entry:
-; CHECK: access_double:
+; CHECK-LABEL: access_double:
 ; CHECK: ld {{[0-9]+}}, .LC{{[0-9]+}}@toc(2)
   %cmp = fcmp oeq double %a, 2.000000e+00
   %conv = zext i1 %cmp to i32 
@@ -43,7 +43,7 @@ entry:
 
 define i32 @access_double_array(double %a, i32 %i) nounwind readonly {
 entry:
-; CHECK: access_double_array:
+; CHECK-LABEL: access_double_array:
   %idxprom = sext i32 %i to i64
   %arrayidx = getelementptr inbounds [32 x double]* @double_array, i64 0, i64 %idxprom
   %0 = load double* %arrayidx, align 8
diff --git a/test/CodeGen/PowerPC/pr13891.ll b/test/CodeGen/PowerPC/pr13891.ll
index 3ae7385..4be65dd 100644
--- a/test/CodeGen/PowerPC/pr13891.ll
+++ b/test/CodeGen/PowerPC/pr13891.ll
@@ -5,7 +5,7 @@ target triple = "powerpc64-unknown-linux-gnu"
 %struct.foo = type { i8, i8 }
 
 define void @_Z5check3foos(%struct.foo* nocapture byval %f, i16 signext %i) noinline {
-; CHECK: _Z5check3foos:
+; CHECK-LABEL: _Z5check3foos:
 ; CHECK: sth 3, {{[0-9]+}}(1)
 ; CHECK: lha {{[0-9]+}}, {{[0-9]+}}(1)
 entry:
diff --git a/test/CodeGen/PowerPC/rounding-ops.ll b/test/CodeGen/PowerPC/rounding-ops.ll
index fa57ee2..2c02900 100644
--- a/test/CodeGen/PowerPC/rounding-ops.ll
+++ b/test/CodeGen/PowerPC/rounding-ops.ll
@@ -10,7 +10,7 @@ define float @test1(float %x) nounwind  {
 ; CHECK-LABEL: test1:
 ; CHECK: frim 1, 1
 
-; CHECK-FM: test1:
+; CHECK-FM-LABEL: test1:
 ; CHECK-FM: frim 1, 1
 }
 
@@ -23,7 +23,7 @@ define double @test2(double %x) nounwind  {
 ; CHECK-LABEL: test2:
 ; CHECK: frim 1, 1
 
-; CHECK-FM: test2:
+; CHECK-FM-LABEL: test2:
 ; CHECK-FM: frim 1, 1
 }
 
@@ -36,7 +36,7 @@ define float @test3(float %x) nounwind  {
 ; CHECK-LABEL: test3:
 ; CHECK-NOT: frin
 
-; CHECK-FM: test3:
+; CHECK-FM-LABEL: test3:
 ; CHECK-FM: frin 1, 1
 }
 
@@ -49,7 +49,7 @@ define double @test4(double %x) nounwind  {
 ; CHECK-LABEL: test4:
 ; CHECK-NOT: frin
 
-; CHECK-FM: test4:
+; CHECK-FM-LABEL: test4:
 ; CHECK-FM: frin 1, 1
 }
 
@@ -62,7 +62,7 @@ define float @test5(float %x) nounwind  {
 ; CHECK-LABEL: test5:
 ; CHECK: frip 1, 1
 
-; CHECK-FM: test5:
+; CHECK-FM-LABEL: test5:
 ; CHECK-FM: frip 1, 1
 }
 
@@ -75,7 +75,7 @@ define double @test6(double %x) nounwind  {
 ; CHECK-LABEL: test6:
 ; CHECK: frip 1, 1
 
-; CHECK-FM: test6:
+; CHECK-FM-LABEL: test6:
 ; CHECK-FM: frip 1, 1
 }
 
@@ -88,7 +88,7 @@ define float @test9(float %x) nounwind  {
 ; CHECK-LABEL: test9:
 ; CHECK: friz 1, 1
 
-; CHECK-FM: test9:
+; CHECK-FM-LABEL: test9:
 ; CHECK-FM: friz 1, 1
 }
 
@@ -101,7 +101,7 @@ define double @test10(double %x) nounwind  {
 ; CHECK-LABEL: test10:
 ; CHECK: friz 1, 1
 
-; CHECK-FM: test10:
+; CHECK-FM-LABEL: test10:
 ; CHECK-FM: friz 1, 1
 }
 
@@ -115,7 +115,7 @@ define void @test11(float %x, float* %y) nounwind  {
 ; CHECK-LABEL: test11:
 ; CHECK-NOT: frin
 
-; CHECK-FM: test11:
+; CHECK-FM-LABEL: test11:
 ; CHECK-FM: frin [[R2:[0-9]+]], [[R1:[0-9]+]]
 ; CHECK-FM: fcmpu [[CR:[0-9]+]], [[R2]], [[R1]]
 ; CHECK-FM: beq [[CR]], .LBB[[BB:[0-9]+]]_2
@@ -134,7 +134,7 @@ define void @test12(double %x, double* %y) nounwind  {
 ; CHECK-LABEL: test12:
 ; CHECK-NOT: frin
 
-; CHECK-FM: test12:
+; CHECK-FM-LABEL: test12:
 ; CHECK-FM: frin [[R2:[0-9]+]], [[R1:[0-9]+]]
 ; CHECK-FM: fcmpu [[CR:[0-9]+]], [[R2]], [[R1]]
 ; CHECK-FM: beq [[CR]], .LBB[[BB:[0-9]+]]_2
diff --git a/test/CodeGen/PowerPC/svr4-redzone.ll b/test/CodeGen/PowerPC/svr4-redzone.ll
index 91ff579..7c51b67 100644
--- a/test/CodeGen/PowerPC/svr4-redzone.ll
+++ b/test/CodeGen/PowerPC/svr4-redzone.ll
@@ -7,11 +7,11 @@ entry:
 	%0 = add i32 1, 2
 	ret void
 }
-; PPC32: regalloc:
+; PPC32-LABEL: regalloc:
 ; PPC32-NOT: stwu 1, -{{[0-9]+}}(1)
 ; PPC32: blr
 
-; PPC64: regalloc:
+; PPC64-LABEL: regalloc:
 ; PPC64-NOT: stdu 1, -{{[0-9]+}}(1)
 ; PPC64: blr
 
@@ -20,10 +20,10 @@ entry:
 	%0 = alloca i8, i32 4
 	ret void
 }
-; PPC32: smallstack:
+; PPC32-LABEL: smallstack:
 ; PPC32: stwu 1, -16(1)
 
-; PPC64: smallstack:
+; PPC64-LABEL: smallstack:
 ; PPC64-NOT: stdu 1, -{{[0-9]+}}(1)
 ; PPC64: blr
 
@@ -32,8 +32,8 @@ entry:
 	%0 = alloca i8, i32 230
 	ret void
 }
-; PPC32: bigstack:
+; PPC32-LABEL: bigstack:
 ; PPC32: stwu 1, -240(1)
 
-; PPC64: bigstack:
+; PPC64-LABEL: bigstack:
 ; PPC64: stdu 1, -352(1)
diff --git a/test/CodeGen/PowerPC/tls-2.ll b/test/CodeGen/PowerPC/tls-2.ll
index 20d8fe4..c2faf90 100644
--- a/test/CodeGen/PowerPC/tls-2.ll
+++ b/test/CodeGen/PowerPC/tls-2.ll
@@ -4,7 +4,7 @@ target triple = "powerpc64-unknown-freebsd10.0"
 
 @a = thread_local global i32 0, align 4
 
-;CHECK:          localexec:
+;CHECK-LABEL:          localexec:
 define i32 @localexec() nounwind {
 entry:
 ;CHECK:          addis [[REG1:[0-9]+]], 13, a@tprel@ha
diff --git a/test/CodeGen/PowerPC/tls.ll b/test/CodeGen/PowerPC/tls.ll
index 2daa60a..4e0a822 100644
--- a/test/CodeGen/PowerPC/tls.ll
+++ b/test/CodeGen/PowerPC/tls.ll
@@ -5,8 +5,8 @@ target triple = "powerpc64-unknown-freebsd10.0"
 
 @a = thread_local global i32 0, align 4
 
-;OPT0:          localexec:
-;OPT1:          localexec:
+;OPT0-LABEL:          localexec:
+;OPT1-LABEL:          localexec:
 define i32 @localexec() nounwind {
 entry:
 ;OPT0:          addis [[REG1:[0-9]+]], 13, a@tprel@ha
diff --git a/test/CodeGen/PowerPC/vec_cmp.ll b/test/CodeGen/PowerPC/vec_cmp.ll
index eb41667..83e0e02 100644
--- a/test/CodeGen/PowerPC/vec_cmp.ll
+++ b/test/CodeGen/PowerPC/vec_cmp.ll
@@ -14,7 +14,7 @@ define <2 x i8> @v2si8_cmp(<2 x i8> %x, <2 x i8> %y) nounwind readnone {
   %sext = sext <2 x i1> %cmp to <2 x i8>
   ret <2 x i8> %sext
 }
-; CHECK: v2si8_cmp:
+; CHECK-LABEL: v2si8_cmp:
 ; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
 
@@ -23,7 +23,7 @@ define <4 x i8> @v4si8_cmp(<4 x i8> %x, <4 x i8> %y) nounwind readnone {
   %sext = sext <4 x i1> %cmp to <4 x i8>
   ret <4 x i8> %sext
 }
-; CHECK: v4si8_cmp:
+; CHECK-LABEL: v4si8_cmp:
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
 
@@ -32,7 +32,7 @@ define <8 x i8> @v8si8_cmp(<8 x i8> %x, <8 x i8> %y) nounwind readnone {
   %sext = sext <8 x i1> %cmp to <8 x i8>
   ret <8 x i8> %sext
 }
-; CHECK: v8si8_cmp:
+; CHECK-LABEL: v8si8_cmp:
 ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
 
@@ -43,7 +43,7 @@ define <16 x i8> @v16si8_cmp_eq(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK: v16si8_cmp_eq:
+; CHECK-LABEL: v16si8_cmp_eq:
 ; CHECK: vcmpequb 2, 2, 3
 
 define <16 x i8> @v16si8_cmp_ne(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
@@ -52,7 +52,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK:     v16si8_cmp_ne:
+; CHECK-LABEL:     v16si8_cmp_ne:
 ; CHECK:     vcmpequb [[RET:[0-9]+]], 2, 3
 ; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
 
@@ -62,7 +62,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK:      v16si8_cmp_le:
+; CHECK-LABEL:      v16si8_cmp_le:
 ; CHECK:      vcmpequb [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtsb [[RCMPLE:[0-9]+]], 3, 2
 ; CHECK-NEXT: vor      2, [[RCMPLE]], [[RCMPEQ]]
@@ -73,7 +73,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK:      v16ui8_cmp_le:
+; CHECK-LABEL:      v16ui8_cmp_le:
 ; CHECK:      vcmpequb [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtub [[RCMPLE:[0-9]+]], 3, 2
 ; CHECK-NEXT: vor      2, [[RCMPLE]], [[RCMPEQ]]
@@ -84,7 +84,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK: v16si8_cmp_lt:
+; CHECK-LABEL: v16si8_cmp_lt:
 ; CHECK: vcmpgtsb 2, 3, 2
 
 define <16 x i8> @v16ui8_cmp_lt(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
@@ -93,7 +93,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK: v16ui8_cmp_lt:
+; CHECK-LABEL: v16ui8_cmp_lt:
 ; CHECK: vcmpgtub 2, 3, 2
 
 define <16 x i8> @v16si8_cmp_gt(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
@@ -102,7 +102,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK: v16si8_cmp_gt:
+; CHECK-LABEL: v16si8_cmp_gt:
 ; CHECK: vcmpgtsb 2, 2, 3
 
 define <16 x i8> @v16ui8_cmp_gt(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
@@ -111,7 +111,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK: v16ui8_cmp_gt:
+; CHECK-LABEL: v16ui8_cmp_gt:
 ; CHECK: vcmpgtub 2, 2, 3
 
 define <16 x i8> @v16si8_cmp_ge(<16 x i8> %x, <16 x i8> %y) nounwind readnone {
@@ -120,7 +120,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK:      v16si8_cmp_ge:
+; CHECK-LABEL:      v16si8_cmp_ge:
 ; CHECK:      vcmpequb [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtsb [[RCMPGT:[0-9]+]], 2, 3
 ; CHECK-NEXT: vor      2, [[RCMPGT]], [[RCMPEQ]]
@@ -131,7 +131,7 @@ entry:
   %sext = sext <16 x i1> %cmp to <16 x i8>
   ret <16 x i8> %sext
 }
-; CHECK:      v16ui8_cmp_ge:
+; CHECK-LABEL:      v16ui8_cmp_ge:
 ; CHECK:      vcmpequb [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtub [[RCMPGT:[0-9]+]], 2, 3
 ; CHECK-NEXT: vor      2, [[RCMPGT]], [[RCMPEQ]]
@@ -142,7 +142,7 @@ define <32 x i8> @v32si8_cmp(<32 x i8> %x, <32 x i8> %y) nounwind readnone {
   %sext = sext <32 x i1> %cmp to <32 x i8>
   ret <32 x i8> %sext
 }
-; CHECK: v32si8_cmp:
+; CHECK-LABEL: v32si8_cmp:
 ; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequb {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
@@ -152,7 +152,7 @@ define <2 x i16> @v2si16_cmp(<2 x i16> %x, <2 x i16> %y) nounwind readnone {
   %sext = sext <2 x i1> %cmp to <2 x i16>
   ret <2 x i16> %sext
 }
-; CHECK: v2si16_cmp:
+; CHECK-LABEL: v2si16_cmp:
 ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
 
@@ -161,7 +161,7 @@ define <4 x i16> @v4si16_cmp(<4 x i16> %x, <4 x i16> %y) nounwind readnone {
   %sext = sext <4 x i1> %cmp to <4 x i16>
   ret <4 x i16> %sext
 }
-; CHECK: v4si16_cmp:
+; CHECK-LABEL: v4si16_cmp:
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
 
@@ -173,7 +173,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK: v8si16_cmp_eq:
+; CHECK-LABEL: v8si16_cmp_eq:
 ; CHECK: vcmpequh 2, 2, 3
 
 define <8 x i16> @v8si16_cmp_ne(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
@@ -182,7 +182,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK:      v8si16_cmp_ne:
+; CHECK-LABEL:      v8si16_cmp_ne:
 ; CHECK:      vcmpequh [[RET:[0-9]+]], 2, 3
 ; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
 
@@ -192,7 +192,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK:      v8si16_cmp_le:
+; CHECK-LABEL:      v8si16_cmp_le:
 ; CHECK:      vcmpequh [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtsh [[RCMPLE:[0-9]+]], 3, 2
 ; CHECK-NEXT: vor      2, [[RCMPLE]], [[RCMPEQ]]
@@ -203,7 +203,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK:      v8ui16_cmp_le:
+; CHECK-LABEL:      v8ui16_cmp_le:
 ; CHECK:      vcmpequh [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtuh [[RCMPLE:[0-9]+]], 3, 2
 ; CHECK-NEXT: vor      2, [[RCMPLE]], [[RCMPEQ]]
@@ -214,7 +214,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK: v8si16_cmp_lt:
+; CHECK-LABEL: v8si16_cmp_lt:
 ; CHECK: vcmpgtsh 2, 3, 2
 
 define <8 x i16> @v8ui16_cmp_lt(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
@@ -223,7 +223,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK: v8ui16_cmp_lt:
+; CHECK-LABEL: v8ui16_cmp_lt:
 ; CHECK: vcmpgtuh 2, 3, 2
 
 define <8 x i16> @v8si16_cmp_gt(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
@@ -232,7 +232,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK: v8si16_cmp_gt:
+; CHECK-LABEL: v8si16_cmp_gt:
 ; CHECK: vcmpgtsh 2, 2, 3
 
 define <8 x i16> @v8ui16_cmp_gt(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
@@ -241,7 +241,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK: v8ui16_cmp_gt:
+; CHECK-LABEL: v8ui16_cmp_gt:
 ; CHECK: vcmpgtuh 2, 2, 3
 
 define <8 x i16> @v8si16_cmp_ge(<8 x i16> %x, <8 x i16> %y) nounwind readnone {
@@ -250,7 +250,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK:      v8si16_cmp_ge:
+; CHECK-LABEL:      v8si16_cmp_ge:
 ; CHECK:      vcmpequh [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtsh [[RCMPGT:[0-9]+]], 2, 3
 ; CHECK-NEXT: vor      2, [[RCMPGT]], [[RCMPEQ]]
@@ -261,7 +261,7 @@ entry:
   %sext = sext <8 x i1> %cmp to <8 x i16>
   ret <8 x i16> %sext
 }
-; CHECK:      v8ui16_cmp_ge:
+; CHECK-LABEL:      v8ui16_cmp_ge:
 ; CHECK:      vcmpequh [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtuh [[RCMPGT:[0-9]+]], 2, 3
 ; CHECK-NEXT: vor      2, [[RCMPGT]], [[RCMPEQ]]
@@ -272,7 +272,7 @@ define <16 x i16> @v16si16_cmp(<16 x i16> %x, <16 x i16> %y) nounwind readnone {
   %sext = sext <16 x i1> %cmp to <16 x i16>
   ret <16 x i16> %sext
 }
-; CHECK: v16si16_cmp:
+; CHECK-LABEL: v16si16_cmp:
 ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
@@ -282,7 +282,7 @@ define <32 x i16> @v32si16_cmp(<32 x i16> %x, <32 x i16> %y) nounwind readnone {
   %sext = sext <32 x i1> %cmp to <32 x i16>
   ret <32 x i16> %sext
 }
-; CHECK: v32si16_cmp:
+; CHECK-LABEL: v32si16_cmp:
 ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequh {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
@@ -294,7 +294,7 @@ define <2 x i32> @v2si32_cmp(<2 x i32> %x, <2 x i32> %y) nounwind readnone {
   %sext = sext <2 x i1> %cmp to <2 x i32>
   ret <2 x i32> %sext
 }
-; CHECK: v2si32_cmp:
+; CHECK-LABEL: v2si32_cmp:
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
 
@@ -306,7 +306,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK: v4si32_cmp_eq:
+; CHECK-LABEL: v4si32_cmp_eq:
 ; CHECK: vcmpequw 2, 2, 3
 
 define <4 x i32> @v4si32_cmp_ne(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
@@ -315,7 +315,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK:      v4si32_cmp_ne:
+; CHECK-LABEL:      v4si32_cmp_ne:
 ; CHECK:      vcmpequw [[RCMP:[0-9]+]], 2, 3
 ; CHECK-NEXT: vnor     2, [[RCMP]], [[RCMP]]
 
@@ -325,7 +325,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK:      v4si32_cmp_le:
+; CHECK-LABEL:      v4si32_cmp_le:
 ; CHECK:      vcmpequw [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtsw [[RCMPLE:[0-9]+]], 3, 2
 ; CHECK-NEXT: vor      2, [[RCMPLE]], [[RCMPEQ]]
@@ -336,7 +336,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK:      v4ui32_cmp_le:
+; CHECK-LABEL:      v4ui32_cmp_le:
 ; CHECK:      vcmpequw [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtuw [[RCMPLE:[0-9]+]], 3, 2
 ; CHECK-NEXT: vor      2, [[RCMPLE]], [[RCMPEQ]]
@@ -347,7 +347,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK: v4si32_cmp_lt:
+; CHECK-LABEL: v4si32_cmp_lt:
 ; CHECK: vcmpgtsw 2, 3, 2
 
 define <4 x i32> @v4ui32_cmp_lt(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
@@ -356,7 +356,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK: v4ui32_cmp_lt:
+; CHECK-LABEL: v4ui32_cmp_lt:
 ; CHECK: vcmpgtuw 2, 3, 2
 
 define <4 x i32> @v4si32_cmp_gt(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
@@ -365,7 +365,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK: v4si32_cmp_gt:
+; CHECK-LABEL: v4si32_cmp_gt:
 ; CHECK: vcmpgtsw 2, 2, 3
 
 define <4 x i32> @v4ui32_cmp_gt(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
@@ -374,7 +374,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK: v4ui32_cmp_gt:
+; CHECK-LABEL: v4ui32_cmp_gt:
 ; CHECK: vcmpgtuw 2, 2, 3
 
 define <4 x i32> @v4si32_cmp_ge(<4 x i32> %x, <4 x i32> %y) nounwind readnone {
@@ -383,7 +383,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK:      v4si32_cmp_ge:
+; CHECK-LABEL:      v4si32_cmp_ge:
 ; CHECK:      vcmpequw [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtsw [[RCMPGT:[0-9]+]], 2, 3
 ; CHECK-NEXT: vor      2, [[RCMPGT]], [[RCMPEQ]]
@@ -394,7 +394,7 @@ entry:
   %sext = sext <4 x i1> %cmp to <4 x i32>
   ret <4 x i32> %sext
 }
-; CHECK:      v4ui32_cmp_ge:
+; CHECK-LABEL:      v4ui32_cmp_ge:
 ; CHECK:      vcmpequw [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtuw [[RCMPGT:[0-9]+]], 2, 3
 ; CHECK-NEXT: vor      2, [[RCMPGT]], [[RCMPEQ]]
@@ -405,7 +405,7 @@ define <8 x i32> @v8si32_cmp(<8 x i32> %x, <8 x i32> %y) nounwind readnone {
   %sext = sext <8 x i1> %cmp to <8 x i32>
   ret <8 x i32> %sext
 }
-; CHECK: v8si32_cmp:
+; CHECK-LABEL: v8si32_cmp:
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
@@ -415,7 +415,7 @@ define <16 x i32> @v16si32_cmp(<16 x i32> %x, <16 x i32> %y) nounwind readnone {
   %sext = sext <16 x i1> %cmp to <16 x i32>
   ret <16 x i32> %sext
 }
-; CHECK: v16si32_cmp:
+; CHECK-LABEL: v16si32_cmp:
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
@@ -427,7 +427,7 @@ define <32 x i32> @v32si32_cmp(<32 x i32> %x, <32 x i32> %y) nounwind readnone {
   %sext = sext <32 x i1> %cmp to <32 x i32>
   ret <32 x i32> %sext
 }
-; CHECK: v32si32_cmp:
+; CHECK-LABEL: v32si32_cmp:
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpequw {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
@@ -445,7 +445,7 @@ entry:
   %0 = bitcast <2 x i32> %sext to <2 x float>
   ret <2 x float> %0
 }
-; CHECK: v2f32_cmp:
+; CHECK-LABEL: v2f32_cmp:
 ; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 
 
@@ -458,7 +458,7 @@ entry:
   %0 = bitcast <4 x i32> %sext to <4 x float>
   ret <4 x float> %0
 }
-; CHECK: v4f32_cmp_eq:
+; CHECK-LABEL: v4f32_cmp_eq:
 ; CHECK: vcmpeqfp 2, 2, 3
 
 define <4 x float> @v4f32_cmp_ne(<4 x float> %x, <4 x float> %y) nounwind readnone {
@@ -468,7 +468,7 @@ entry:
   %0 = bitcast <4 x i32> %sext to <4 x float>
   ret <4 x float> %0
 }
-; CHECK:      v4f32_cmp_ne:
+; CHECK-LABEL:      v4f32_cmp_ne:
 ; CHECK:      vcmpeqfp [[RET:[0-9]+]], 2, 3
 ; CHECK-NEXT: vnor     2, [[RET]], [[RET]]
 
@@ -479,7 +479,7 @@ entry:
   %0 = bitcast <4 x i32> %sext to <4 x float>
   ret <4 x float> %0
 }
-; CHECK:      v4f32_cmp_le:
+; CHECK-LABEL:      v4f32_cmp_le:
 ; CHECK:      vcmpeqfp [[RCMPEQ:[0-9]+]], 2, 3
 ; CHECK-NEXT: vcmpgtfp [[RCMPLE:[0-9]+]], 3, 2
 ; CHECK-NEXT: vor      2, [[RCMPLE]], [[RCMPEQ]]
@@ -491,7 +491,7 @@ entry:
   %0 = bitcast <4 x i32> %sext to <4 x float>
   ret <4 x float> %0
 }
-; CHECK: v4f32_cmp_lt:
+; CHECK-LABEL: v4f32_cmp_lt:
 ; CHECK: vcmpgtfp 2, 3, 2
 
 define <4 x float> @v4f32_cmp_ge(<4 x float> %x, <4 x float> %y) nounwind readnone {
@@ -501,7 +501,7 @@ entry:
   %0 = bitcast <4 x i32> %sext to <4 x float>
   ret <4 x float> %0
 }
-; CHECK: v4f32_cmp_ge:
+; CHECK-LABEL: v4f32_cmp_ge:
 ; CHECK: vcmpgefp 2, 2, 3
 
 define <4 x float> @v4f32_cmp_gt(<4 x float> %x, <4 x float> %y) nounwind readnone {
@@ -511,7 +511,7 @@ entry:
   %0 = bitcast <4 x i32> %sext to <4 x float>
   ret <4 x float> %0
 }
-; CHECK: v4f32_cmp_gt:
+; CHECK-LABEL: v4f32_cmp_gt:
 ; CHECK: vcmpgtfp 2, 2, 3
 
 
@@ -522,6 +522,6 @@ entry:
   %0 = bitcast <8 x i32> %sext to <8 x float>
   ret <8 x float> %0
 }
-; CHECK: v8f32_cmp:
+; CHECK-LABEL: v8f32_cmp:
 ; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: vcmpeqfp {{[0-9]+}}, {{[0-9]+}}, {{[0-9]+}}
diff --git a/test/CodeGen/PowerPC/vec_conv.ll b/test/CodeGen/PowerPC/vec_conv.ll
index a475e94..a39ae91 100644
--- a/test/CodeGen/PowerPC/vec_conv.ll
+++ b/test/CodeGen/PowerPC/vec_conv.ll
@@ -17,7 +17,7 @@ entry:
   store <4 x i32> %1, <4 x i32>* %y, align 16
   ret void
 }
-;CHECK: v4f32_to_v4i32:
+;CHECK-LABEL: v4f32_to_v4i32:
 ;CHECK: vctsxs {{[0-9]+}}, {{[0-9]+}}, 0
 
 
@@ -29,7 +29,7 @@ entry:
   store <4 x i32> %1, <4 x i32>* %y, align 16
   ret void
 }
-;CHECK: v4f32_to_v4u32:
+;CHECK-LABEL: v4f32_to_v4u32:
 ;CHECK: vctuxs {{[0-9]+}}, {{[0-9]+}}, 0
 
 
@@ -41,7 +41,7 @@ entry:
   store <4 x float> %1, <4 x float>* %y, align 16
   ret void
 }
-;CHECK: v4i32_to_v4f32:
+;CHECK-LABEL: v4i32_to_v4f32:
 ;CHECK: vcfsx {{[0-9]+}}, {{[0-9]+}}, 0
 
 
@@ -53,5 +53,5 @@ entry:
   store <4 x float> %1, <4 x float>* %y, align 16
   ret void
 }
-;CHECK: v4u32_to_v4f32:
+;CHECK-LABEL: v4u32_to_v4f32:
 ;CHECK: vcfux {{[0-9]+}}, {{[0-9]+}}, 0
diff --git a/test/CodeGen/PowerPC/vec_extload.ll b/test/CodeGen/PowerPC/vec_extload.ll
index 998645d..6373a26 100644
--- a/test/CodeGen/PowerPC/vec_extload.ll
+++ b/test/CodeGen/PowerPC/vec_extload.ll
@@ -14,7 +14,7 @@ define <16 x i8> @v16si8_sext_in_reg(<16 x i8> %a) {
   %c = sext <16 x i4> %b to <16 x i8>
   ret <16 x i8> %c
 }
-; CHECK: v16si8_sext_in_reg:
+; CHECK-LABEL: v16si8_sext_in_reg:
 ; CHECK: vslb
 ; CHECK: vsrab
 ; CHECK: blr 
@@ -26,7 +26,7 @@ define <16 x i8> @v16si8_zext_in_reg(<16 x i8> %a) {
   %c = zext <16 x i4> %b to <16 x i8>
   ret <16 x i8> %c
 }
-; CHECK:      v16si8_zext_in_reg:
+; CHECK-LABEL:      v16si8_zext_in_reg:
 ; CHECK:      vspltisb [[VMASK:[0-9]+]], 15
 ; CHECK-NEXT: vand 2, 2, [[VMASK]]
 
@@ -36,7 +36,7 @@ define <8 x i16> @v8si16_sext_in_reg(<8 x i16> %a) {
   %c = sext <8 x i8> %b to <8 x i16>
   ret <8 x i16> %c
 }
-; CHECK: v8si16_sext_in_reg:
+; CHECK-LABEL: v8si16_sext_in_reg:
 ; CHECK: vslh
 ; CHECK: vsrah
 ; CHECK: blr 
@@ -48,7 +48,7 @@ define <8 x i16> @v8si16_zext_in_reg(<8 x i16> %a) {
   %c = zext <8 x i8> %b to <8 x i16>
   ret <8 x i16> %c
 }
-; CHECK:      v8si16_zext_in_reg:
+; CHECK-LABEL:      v8si16_zext_in_reg:
 ; CHECK:      ld [[RMASKTOC:[0-9]+]], .LC{{[0-9]+}}@toc(2)
 ; CHECK-NEXT: lvx [[VMASK:[0-9]+]], {{[0-9]+}}, [[RMASKTOC]]
 ; CHECK-NEXT: vand 2, 2, [[VMASK]]
@@ -60,7 +60,7 @@ define <4 x i32> @v4si32_sext_in_reg(<4 x i32> %a) {
   %c = sext <4 x i16> %b to <4 x i32>
   ret <4 x i32> %c
 }
-; CHECK: v4si32_sext_in_reg:
+; CHECK-LABEL: v4si32_sext_in_reg:
 ; CHECK: vslw
 ; CHECK: vsraw
 ; CHECK: blr 
@@ -71,7 +71,7 @@ define <4 x i32> @v4si32_zext_in_reg(<4 x i32> %a) {
   %c = zext <4 x i16> %b to <4 x i32>
   ret <4 x i32> %c
 }
-; CHECK:      v4si32_zext_in_reg:
+; CHECK-LABEL:      v4si32_zext_in_reg:
 ; CHECK:      vspltisw [[VMASK:[0-9]+]], -16
 ; CHECK-NEXT: vsrw [[VMASK]], [[VMASK]], [[VMASK]]
 ; CHECK-NEXT: vand 2, 2, [[VMASK]]
diff --git a/test/CodeGen/PowerPC/vec_rounding.ll b/test/CodeGen/PowerPC/vec_rounding.ll
index 7c55638..ace187b 100644
--- a/test/CodeGen/PowerPC/vec_rounding.ll
+++ b/test/CodeGen/PowerPC/vec_rounding.ll
@@ -12,7 +12,7 @@ define <2 x double> @floor_v2f64(<2 x double> %p)
   %t = call <2 x double> @llvm.floor.v2f64(<2 x double> %p)
   ret <2 x double> %t
 }
-; CHECK: floor_v2f64:
+; CHECK-LABEL: floor_v2f64:
 ; CHECK: frim
 ; CHECK: frim
 
@@ -22,7 +22,7 @@ define <4 x double> @floor_v4f64(<4 x double> %p)
   %t = call <4 x double> @llvm.floor.v4f64(<4 x double> %p)
   ret <4 x double> %t
 }
-; CHECK: floor_v4f64:
+; CHECK-LABEL: floor_v4f64:
 ; CHECK: frim
 ; CHECK: frim
 ; CHECK: frim
@@ -34,7 +34,7 @@ define <2 x double> @ceil_v2f64(<2 x double> %p)
   %t = call <2 x double> @llvm.ceil.v2f64(<2 x double> %p)
   ret <2 x double> %t
 }
-; CHECK: ceil_v2f64:
+; CHECK-LABEL: ceil_v2f64:
 ; CHECK: frip
 ; CHECK: frip
 
@@ -44,7 +44,7 @@ define <4 x double> @ceil_v4f64(<4 x double> %p)
   %t = call <4 x double> @llvm.ceil.v4f64(<4 x double> %p)
   ret <4 x double> %t
 }
-; CHECK: ceil_v4f64:
+; CHECK-LABEL: ceil_v4f64:
 ; CHECK: frip
 ; CHECK: frip
 ; CHECK: frip
@@ -56,7 +56,7 @@ define <2 x double> @trunc_v2f64(<2 x double> %p)
   %t = call <2 x double> @llvm.trunc.v2f64(<2 x double> %p)
   ret <2 x double> %t
 }
-; CHECK: trunc_v2f64:
+; CHECK-LABEL: trunc_v2f64:
 ; CHECK: friz
 ; CHECK: friz
 
@@ -66,7 +66,7 @@ define <4 x double> @trunc_v4f64(<4 x double> %p)
   %t = call <4 x double> @llvm.trunc.v4f64(<4 x double> %p)
   ret <4 x double> %t
 }
-; CHECK: trunc_v4f64:
+; CHECK-LABEL: trunc_v4f64:
 ; CHECK: friz
 ; CHECK: friz
 ; CHECK: friz
@@ -78,7 +78,7 @@ define <2 x double> @nearbyint_v2f64(<2 x double> %p)
   %t = call <2 x double> @llvm.nearbyint.v2f64(<2 x double> %p)
   ret <2 x double> %t
 }
-; CHECK: nearbyint_v2f64:
+; CHECK-LABEL: nearbyint_v2f64:
 ; CHECK: bl nearbyint
 ; CHECK: bl nearbyint
 
@@ -88,7 +88,7 @@ define <4 x double> @nearbyint_v4f64(<4 x double> %p)
   %t = call <4 x double> @llvm.nearbyint.v4f64(<4 x double> %p)
   ret <4 x double> %t
 }
-; CHECK: nearbyint_v4f64:
+; CHECK-LABEL: nearbyint_v4f64:
 ; CHECK: bl nearbyint
 ; CHECK: bl nearbyint
 ; CHECK: bl nearbyint
@@ -101,7 +101,7 @@ define <4 x float> @floor_v4f32(<4 x float> %p)
   %t = call <4 x float> @llvm.floor.v4f32(<4 x float> %p)
   ret <4 x float> %t
 }
-; CHECK: floor_v4f32:
+; CHECK-LABEL: floor_v4f32:
 ; CHECK: vrfim
 
 declare <8 x float> @llvm.floor.v8f32(<8 x float> %p)
@@ -110,7 +110,7 @@ define <8 x float> @floor_v8f32(<8 x float> %p)
   %t = call <8 x float> @llvm.floor.v8f32(<8 x float> %p)
   ret <8 x float> %t
 }
-; CHECK: floor_v8f32:
+; CHECK-LABEL: floor_v8f32:
 ; CHECK: vrfim
 ; CHECK: vrfim
 
@@ -120,7 +120,7 @@ define <4 x float> @ceil_v4f32(<4 x float> %p)
   %t = call <4 x float> @llvm.ceil.v4f32(<4 x float> %p)
   ret <4 x float> %t
 }
-; CHECK: ceil_v4f32:
+; CHECK-LABEL: ceil_v4f32:
 ; CHECK: vrfip
 
 declare <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
@@ -129,7 +129,7 @@ define <8 x float> @ceil_v8f32(<8 x float> %p)
   %t = call <8 x float> @llvm.ceil.v8f32(<8 x float> %p)
   ret <8 x float> %t
 }
-; CHECK: ceil_v8f32:
+; CHECK-LABEL: ceil_v8f32:
 ; CHECK: vrfip
 ; CHECK: vrfip
 
@@ -139,7 +139,7 @@ define <4 x float> @trunc_v4f32(<4 x float> %p)
   %t = call <4 x float> @llvm.trunc.v4f32(<4 x float> %p)
   ret <4 x float> %t
 }
-; CHECK: trunc_v4f32:
+; CHECK-LABEL: trunc_v4f32:
 ; CHECK: vrfiz
 
 declare <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
@@ -148,7 +148,7 @@ define <8 x float> @trunc_v8f32(<8 x float> %p)
   %t = call <8 x float> @llvm.trunc.v8f32(<8 x float> %p)
   ret <8 x float> %t
 }
-; CHECK: trunc_v8f32:
+; CHECK-LABEL: trunc_v8f32:
 ; CHECK: vrfiz
 ; CHECK: vrfiz
 
@@ -158,7 +158,7 @@ define <4 x float> @nearbyint_v4f32(<4 x float> %p)
   %t = call <4 x float> @llvm.nearbyint.v4f32(<4 x float> %p)
   ret <4 x float> %t
 }
-; CHECK: nearbyint_v4f32:
+; CHECK-LABEL: nearbyint_v4f32:
 ; CHECK: vrfin
 
 declare <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
@@ -167,6 +167,6 @@ define <8 x float> @nearbyint_v8f32(<8 x float> %p)
   %t = call <8 x float> @llvm.nearbyint.v8f32(<8 x float> %p)
   ret <8 x float> %t
 }
-; CHECK: nearbyint_v8f32:
+; CHECK-LABEL: nearbyint_v8f32:
 ; CHECK: vrfin
 ; CHECK: vrfin
diff --git a/test/CodeGen/PowerPC/vec_sqrt.ll b/test/CodeGen/PowerPC/vec_sqrt.ll
index 055da1a..a85c3ff 100644
--- a/test/CodeGen/PowerPC/vec_sqrt.ll
+++ b/test/CodeGen/PowerPC/vec_sqrt.ll
@@ -18,7 +18,7 @@ entry:
   ret <2 x float> %sqrt
 }
 ; sqrt (<2 x float>) is promoted to sqrt (<4 x float>)
-; CHECK: v2f32_sqrt:
+; CHECK-LABEL: v2f32_sqrt:
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
@@ -29,7 +29,7 @@ entry:
   %sqrt = call <4 x float> @llvm.sqrt.v4f32 (<4 x float> %x)
   ret <4 x float> %sqrt
 }
-; CHECK: v4f32_sqrt:
+; CHECK-LABEL: v4f32_sqrt:
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
@@ -40,7 +40,7 @@ entry:
   %sqrt = call <8 x float> @llvm.sqrt.v8f32 (<8 x float> %x)
   ret <8 x float> %sqrt
 }
-; CHECK: v8f32_sqrt:
+; CHECK-LABEL: v8f32_sqrt:
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrts {{[0-9]+}}, {{[0-9]+}}
@@ -55,7 +55,7 @@ entry:
   %sqrt = call <2 x double> @llvm.sqrt.v2f64 (<2 x double> %x)
   ret <2 x double> %sqrt
 }
-; CHECK: v2f64_sqrt:
+; CHECK-LABEL: v2f64_sqrt:
 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
 
@@ -64,7 +64,7 @@ entry:
   %sqrt = call <4 x double> @llvm.sqrt.v4f64 (<4 x double> %x)
   ret <4 x double> %sqrt
 }
-; CHECK: v4f64_sqrt:
+; CHECK-LABEL: v4f64_sqrt:
 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}
 ; CHECK: fsqrt {{[0-9]+}}, {{[0-9]+}}