Convert CodeGen/*/*.ll tests to use the new CHECK-LABEL for easier debugging. No functionality change and all tests pass after conversion.

This was done with the following sed invocation to catch label lines demarking function boundaries:
    sed -i '' "s/^;\( *\)\([A-Z0-9_]*\):\( *\)test\([A-Za-z0-9_-]*\):\( *\)$/;\1\2-LABEL:\3test\4:\5/g" test/CodeGen/*/*.ll
which was written conservatively to avoid false positives rather than false negatives. I scanned through all the changes and everything looks correct.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186258 91177308-0d34-0410-b5e6-96231b3b80d8

22 files changed, 68 insertions, 68 deletions

diff --git a/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll b/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll
index a18829e..b1cbb36 100644
--- a/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll
+++ b/test/CodeGen/PowerPC/2011-12-08-DemandedBitsMiscompile.ll
@@ -9,7 +9,7 @@ entry:
   store i64 %z2, i64* %xx, align 4
   ret void
 
-; CHECK: test:
+; CHECK-LABEL: test:
 ; CHECK: sldi {{.*}}, {{.*}}, 32
 ; Note: it's okay if someday CodeGen gets smart enough to optimize out
 ; the shift.
diff --git a/test/CodeGen/PowerPC/fma.ll b/test/CodeGen/PowerPC/fma.ll
index a173c91..db19761 100644
--- a/test/CodeGen/PowerPC/fma.ll
+++ b/test/CodeGen/PowerPC/fma.ll
@@ -4,7 +4,7 @@ define double @test_FMADD1(double %A, double %B, double %C) {
 	%D = fmul double %A, %B		; <double> [#uses=1]
 	%E = fadd double %D, %C		; <double> [#uses=1]
 	ret double %E
-; CHECK: test_FMADD1:
+; CHECK-LABEL: test_FMADD1:
 ; CHECK: fmadd
 ; CHECK-NEXT: blr
 }
@@ -13,7 +13,7 @@ define double @test_FMADD2(double %A, double %B, double %C) {
 	%D = fmul double %A, %B		; <double> [#uses=1]
 	%E = fadd double %D, %C		; <double> [#uses=1]
 	ret double %E
-; CHECK: test_FMADD2:
+; CHECK-LABEL: test_FMADD2:
 ; CHECK: fmadd
 ; CHECK-NEXT: blr
 }
@@ -22,7 +22,7 @@ define double @test_FMSUB(double %A, double %B, double %C) {
 	%D = fmul double %A, %B		; <double> [#uses=1]
 	%E = fsub double %D, %C		; <double> [#uses=1]
 	ret double %E
-; CHECK: test_FMSUB:
+; CHECK-LABEL: test_FMSUB:
 ; CHECK: fmsub
 ; CHECK-NEXT: blr
 }
@@ -32,7 +32,7 @@ define double @test_FNMADD1(double %A, double %B, double %C) {
 	%E = fadd double %D, %C		; <double> [#uses=1]
 	%F = fsub double -0.000000e+00, %E		; <double> [#uses=1]
 	ret double %F
-; CHECK: test_FNMADD1:
+; CHECK-LABEL: test_FNMADD1:
 ; CHECK: fnmadd
 ; CHECK-NEXT: blr
 }
@@ -42,7 +42,7 @@ define double @test_FNMADD2(double %A, double %B, double %C) {
 	%E = fadd double %C, %D		; <double> [#uses=1]
 	%F = fsub double -0.000000e+00, %E		; <double> [#uses=1]
 	ret double %F
-; CHECK: test_FNMADD2:
+; CHECK-LABEL: test_FNMADD2:
 ; CHECK: fnmadd
 ; CHECK-NEXT: blr
 }
@@ -51,7 +51,7 @@ define double @test_FNMSUB1(double %A, double %B, double %C) {
 	%D = fmul double %A, %B		; <double> [#uses=1]
 	%E = fsub double %C, %D		; <double> [#uses=1]
 	ret double %E
-; CHECK: test_FNMSUB1:
+; CHECK-LABEL: test_FNMSUB1:
 ; CHECK: fnmsub
 ; CHECK-NEXT: blr
 }
@@ -61,7 +61,7 @@ define double @test_FNMSUB2(double %A, double %B, double %C) {
 	%E = fsub double %D, %C		; <double> [#uses=1]
 	%F = fsub double -0.000000e+00, %E		; <double> [#uses=1]
 	ret double %F
-; CHECK: test_FNMSUB2:
+; CHECK-LABEL: test_FNMSUB2:
 ; CHECK: fnmsub
 ; CHECK-NEXT: blr
 }
@@ -71,7 +71,7 @@ define float @test_FNMSUBS(float %A, float %B, float %C) {
 	%E = fsub float %D, %C		; <float> [#uses=1]
 	%F = fsub float -0.000000e+00, %E		; <float> [#uses=1]
 	ret float %F
-; CHECK: test_FNMSUBS:
+; CHECK-LABEL: test_FNMSUBS:
 ; CHECK: fnmsubs
 ; CHECK-NEXT: blr
 }
diff --git a/test/CodeGen/PowerPC/mcm-1.ll b/test/CodeGen/PowerPC/mcm-1.ll
index a57fb9d..4e31550 100644
--- a/test/CodeGen/PowerPC/mcm-1.ll
+++ b/test/CodeGen/PowerPC/mcm-1.ll
@@ -17,7 +17,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: test_external:
+; CHECK-LABEL: test_external:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
diff --git a/test/CodeGen/PowerPC/mcm-10.ll b/test/CodeGen/PowerPC/mcm-10.ll
index 4bec3e1..b479559 100644
--- a/test/CodeGen/PowerPC/mcm-10.ll
+++ b/test/CodeGen/PowerPC/mcm-10.ll
@@ -16,7 +16,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: test_fn_static:
+; CHECK-LABEL: test_fn_static:
 ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
 ; CHECK: lwz {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
 ; CHECK: stw {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
diff --git a/test/CodeGen/PowerPC/mcm-11.ll b/test/CodeGen/PowerPC/mcm-11.ll
index f2bc4c9..c49e865 100644
--- a/test/CodeGen/PowerPC/mcm-11.ll
+++ b/test/CodeGen/PowerPC/mcm-11.ll
@@ -16,7 +16,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: test_file_static:
+; CHECK-LABEL: test_file_static:
 ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
 ; CHECK: lwz {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
 ; CHECK: stw {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
diff --git a/test/CodeGen/PowerPC/mcm-12.ll b/test/CodeGen/PowerPC/mcm-12.ll
index 911305d..b31b605 100644
--- a/test/CodeGen/PowerPC/mcm-12.ll
+++ b/test/CodeGen/PowerPC/mcm-12.ll
@@ -13,6 +13,6 @@ entry:
 
 ; CHECK: [[VAR:[a-z0-9A-Z_.]+]]:
 ; CHECK: .quad 4562098671269285104
-; CHECK: test_double_const:
+; CHECK-LABEL: test_double_const:
 ; CHECK: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
 ; CHECK: lfd {{[0-9]+}}, [[VAR]]@toc@l([[REG1]])
diff --git a/test/CodeGen/PowerPC/mcm-2.ll b/test/CodeGen/PowerPC/mcm-2.ll
index f0dff4c..d4f40f7 100644
--- a/test/CodeGen/PowerPC/mcm-2.ll
+++ b/test/CodeGen/PowerPC/mcm-2.ll
@@ -17,7 +17,7 @@ entry:
   ret i32 %0
 }
 
-; MEDIUM: test_fn_static:
+; MEDIUM-LABEL: test_fn_static:
 ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
 ; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]])
@@ -26,7 +26,7 @@ entry:
 ; MEDIUM: .local [[VAR]]
 ; MEDIUM: .comm [[VAR]],4,4
 
-; LARGE: test_fn_static:
+; LARGE-LABEL: test_fn_static:
 ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
 ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
 ; LARGE: lwz {{[0-9]+}}, 0([[REG2]])
diff --git a/test/CodeGen/PowerPC/mcm-3.ll b/test/CodeGen/PowerPC/mcm-3.ll
index b790550..ce151fb 100644
--- a/test/CodeGen/PowerPC/mcm-3.ll
+++ b/test/CodeGen/PowerPC/mcm-3.ll
@@ -17,7 +17,7 @@ entry:
   ret i32 %0
 }
 
-; MEDIUM: test_file_static:
+; MEDIUM-LABEL: test_file_static:
 ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
 ; MEDIUM: lwz {{[0-9]+}}, 0([[REG2]])
@@ -28,7 +28,7 @@ entry:
 ; MEDIUM: [[VAR]]:
 ; MEDIUM: .long 5
 
-; LARGE: test_file_static:
+; LARGE-LABEL: test_file_static:
 ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR:[a-z0-9A-Z_.]+]]@toc@ha
 ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
 ; LARGE: lwz {{[0-9]+}}, 0([[REG2]])
diff --git a/test/CodeGen/PowerPC/mcm-4.ll b/test/CodeGen/PowerPC/mcm-4.ll
index 8150f91..7d7b132 100644
--- a/test/CodeGen/PowerPC/mcm-4.ll
+++ b/test/CodeGen/PowerPC/mcm-4.ll
@@ -14,14 +14,14 @@ entry:
 
 ; MEDIUM: [[VAR:[a-z0-9A-Z_.]+]]:
 ; MEDIUM: .quad 4562098671269285104
-; MEDIUM: test_double_const:
+; MEDIUM-LABEL: test_double_const:
 ; MEDIUM: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
 ; MEDIUM: addi [[REG2:[0-9]+]], [[REG1]], [[VAR]]@toc@l
 ; MEDIUM: lfd {{[0-9]+}}, 0([[REG2]])
 
 ; LARGE: [[VAR:[a-z0-9A-Z_.]+]]:
 ; LARGE: .quad 4562098671269285104
-; LARGE: test_double_const:
+; LARGE-LABEL: test_double_const:
 ; LARGE: addis [[REG1:[0-9]+]], 2, [[VAR]]@toc@ha
 ; LARGE: ld [[REG2:[0-9]+]], [[VAR]]@toc@l([[REG1]])
 ; LARGE: lfd {{[0-9]+}}, 0([[REG2]])
diff --git a/test/CodeGen/PowerPC/mcm-5.ll b/test/CodeGen/PowerPC/mcm-5.ll
index 1be27b7..92ddeca 100644
--- a/test/CodeGen/PowerPC/mcm-5.ll
+++ b/test/CodeGen/PowerPC/mcm-5.ll
@@ -51,7 +51,7 @@ sw.epilog:                                        ; preds = %sw.bb3, %sw.default
   ret i32 %5
 }
 
-; CHECK: test_jump_table:
+; CHECK-LABEL: test_jump_table:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: ldx {{[0-9]+}}, {{[0-9]+}}, [[REG2]]
diff --git a/test/CodeGen/PowerPC/mcm-6.ll b/test/CodeGen/PowerPC/mcm-6.ll
index 35efaaa..f7838b4 100644
--- a/test/CodeGen/PowerPC/mcm-6.ll
+++ b/test/CodeGen/PowerPC/mcm-6.ll
@@ -17,7 +17,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: test_tentative:
+; CHECK-LABEL: test_tentative:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
diff --git a/test/CodeGen/PowerPC/mcm-7.ll b/test/CodeGen/PowerPC/mcm-7.ll
index 0dd39ee..7caa13b 100644
--- a/test/CodeGen/PowerPC/mcm-7.ll
+++ b/test/CodeGen/PowerPC/mcm-7.ll
@@ -18,7 +18,7 @@ entry:
 
 declare signext i32 @foo(i32 signext)
 
-; CHECK: test_fnaddr:
+; CHECK-LABEL: test_fnaddr:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: .section .toc
diff --git a/test/CodeGen/PowerPC/mcm-8.ll b/test/CodeGen/PowerPC/mcm-8.ll
index 3ece786..643548f 100644
--- a/test/CodeGen/PowerPC/mcm-8.ll
+++ b/test/CodeGen/PowerPC/mcm-8.ll
@@ -16,7 +16,7 @@ entry:
   ret i8 %1
 }
 
-; CHECK: test_avext:
+; CHECK-LABEL: test_avext:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: lbz {{[0-9]+}}, 0([[REG2]])
diff --git a/test/CodeGen/PowerPC/mcm-9.ll b/test/CodeGen/PowerPC/mcm-9.ll
index f366f45..e587f61 100644
--- a/test/CodeGen/PowerPC/mcm-9.ll
+++ b/test/CodeGen/PowerPC/mcm-9.ll
@@ -18,7 +18,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: test_external:
+; CHECK-LABEL: test_external:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
diff --git a/test/CodeGen/PowerPC/mcm-default.ll b/test/CodeGen/PowerPC/mcm-default.ll
index 19de253..8d4ff14 100644
--- a/test/CodeGen/PowerPC/mcm-default.ll
+++ b/test/CodeGen/PowerPC/mcm-default.ll
@@ -16,7 +16,7 @@ entry:
   ret i32 %0
 }
 
-; CHECK: test_external:
+; CHECK-LABEL: test_external:
 ; CHECK: addis [[REG1:[0-9]+]], 2, .LC[[TOCNUM:[0-9]+]]@toc@ha
 ; CHECK: ld [[REG2:[0-9]+]], .LC[[TOCNUM]]@toc@l([[REG1]])
 ; CHECK: lwz {{[0-9]+}}, 0([[REG2]])
diff --git a/test/CodeGen/PowerPC/misched-inorder-latency.ll b/test/CodeGen/PowerPC/misched-inorder-latency.ll
index 8fae7ad..b259ff1 100644
--- a/test/CodeGen/PowerPC/misched-inorder-latency.ll
+++ b/test/CodeGen/PowerPC/misched-inorder-latency.ll
@@ -6,7 +6,7 @@ target triple = "powerpc64-bgq-linux"
 
 ; %val1 is a load live out of %entry. It should be hoisted
 ; above the add.
-; CHECK: testload:
+; CHECK-LABEL: testload:
 ; CHECK: %entry
 ; CHECK: lwz
 ; CHECK: addi
@@ -34,7 +34,7 @@ end:
 ; The prefetch gets a default latency of 3 cycles and should be hoisted
 ; above the add.
 ;
-; CHECK: testprefetch:
+; CHECK-LABEL: testprefetch:
 ; CHECK: %entry
 ; CHECK: dcbt
 ; CHECK: addi
diff --git a/test/CodeGen/PowerPC/ppc64-calls.ll b/test/CodeGen/PowerPC/ppc64-calls.ll
index c382edb..1f3bb71 100644
--- a/test/CodeGen/PowerPC/ppc64-calls.ll
+++ b/test/CodeGen/PowerPC/ppc64-calls.ll
@@ -12,7 +12,7 @@ define weak void @foo_weak() nounwind {
 
 ; Calls to local function does not require the TOC restore 'nop'
 define void @test_direct() nounwind readnone {
-; CHECK: test_direct:
+; CHECK-LABEL: test_direct:
   tail call void @foo() nounwind
 ; CHECK: bl foo
 ; CHECK-NOT: nop
@@ -22,7 +22,7 @@ define void @test_direct() nounwind readnone {
 ; Calls to weak function requires a TOC restore 'nop' because they
 ; may be overridden in a different module.
 define void @test_weak() nounwind readnone {
-; CHECK: test_weak:
+; CHECK-LABEL: test_weak:
   tail call void @foo_weak() nounwind
 ; CHECK: bl foo
 ; CHECK-NEXT: nop
@@ -31,7 +31,7 @@ define void @test_weak() nounwind readnone {
 
 ; Indirect calls requires a full stub creation
 define void @test_indirect(void ()* nocapture %fp) nounwind {
-; CHECK: test_indirect:
+; CHECK-LABEL: test_indirect:
   tail call void %fp() nounwind
 ; CHECK: ld [[FP:[0-9]+]], 0(3)
 ; CHECK: ld 11, 16(3)
@@ -44,7 +44,7 @@ define void @test_indirect(void ()* nocapture %fp) nounwind {
 
 ; Absolute vales should be have the TOC restore 'nop'
 define void @test_abs() nounwind {
-; CHECK: test_abs:
+; CHECK-LABEL: test_abs:
   tail call void inttoptr (i64 1024 to void ()*)() nounwind
 ; CHECK: bla 1024
 ; CHECK-NEXT: nop
@@ -55,7 +55,7 @@ declare double @sin(double) nounwind
 
 ; External functions call should also have a 'nop'
 define double @test_external(double %x) nounwind {
-; CHECK: test_external:
+; CHECK-LABEL: test_external:
   %call = tail call double @sin(double %x) nounwind
 ; CHECK: bl sin
 ; CHECK-NEXT: nop
diff --git a/test/CodeGen/PowerPC/rounding-ops.ll b/test/CodeGen/PowerPC/rounding-ops.ll
index 2b5e1c9..fa57ee2 100644
--- a/test/CodeGen/PowerPC/rounding-ops.ll
+++ b/test/CodeGen/PowerPC/rounding-ops.ll
@@ -7,7 +7,7 @@ define float @test1(float %x) nounwind  {
   %call = tail call float @floorf(float %x) nounwind readnone
   ret float %call
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK: frim 1, 1
 
 ; CHECK-FM: test1:
@@ -20,7 +20,7 @@ define double @test2(double %x) nounwind  {
   %call = tail call double @floor(double %x) nounwind readnone
   ret double %call
 
-; CHECK: test2:
+; CHECK-LABEL: test2:
 ; CHECK: frim 1, 1
 
 ; CHECK-FM: test2:
@@ -33,7 +33,7 @@ define float @test3(float %x) nounwind  {
   %call = tail call float @nearbyintf(float %x) nounwind readnone
   ret float %call
 
-; CHECK: test3:
+; CHECK-LABEL: test3:
 ; CHECK-NOT: frin
 
 ; CHECK-FM: test3:
@@ -46,7 +46,7 @@ define double @test4(double %x) nounwind  {
   %call = tail call double @nearbyint(double %x) nounwind readnone
   ret double %call
 
-; CHECK: test4:
+; CHECK-LABEL: test4:
 ; CHECK-NOT: frin
 
 ; CHECK-FM: test4:
@@ -59,7 +59,7 @@ define float @test5(float %x) nounwind  {
   %call = tail call float @ceilf(float %x) nounwind readnone
   ret float %call
 
-; CHECK: test5:
+; CHECK-LABEL: test5:
 ; CHECK: frip 1, 1
 
 ; CHECK-FM: test5:
@@ -72,7 +72,7 @@ define double @test6(double %x) nounwind  {
   %call = tail call double @ceil(double %x) nounwind readnone
   ret double %call
 
-; CHECK: test6:
+; CHECK-LABEL: test6:
 ; CHECK: frip 1, 1
 
 ; CHECK-FM: test6:
@@ -85,7 +85,7 @@ define float @test9(float %x) nounwind  {
   %call = tail call float @truncf(float %x) nounwind readnone
   ret float %call
 
-; CHECK: test9:
+; CHECK-LABEL: test9:
 ; CHECK: friz 1, 1
 
 ; CHECK-FM: test9:
@@ -98,7 +98,7 @@ define double @test10(double %x) nounwind  {
   %call = tail call double @trunc(double %x) nounwind readnone
   ret double %call
 
-; CHECK: test10:
+; CHECK-LABEL: test10:
 ; CHECK: friz 1, 1
 
 ; CHECK-FM: test10:
@@ -112,7 +112,7 @@ define void @test11(float %x, float* %y) nounwind  {
   store float %call, float* %y
   ret void
 
-; CHECK: test11:
+; CHECK-LABEL: test11:
 ; CHECK-NOT: frin
 
 ; CHECK-FM: test11:
@@ -131,7 +131,7 @@ define void @test12(double %x, double* %y) nounwind  {
   store double %call, double* %y
   ret void
 
-; CHECK: test12:
+; CHECK-LABEL: test12:
 ; CHECK-NOT: frin
 
 ; CHECK-FM: test12:
diff --git a/test/CodeGen/PowerPC/vaddsplat.ll b/test/CodeGen/PowerPC/vaddsplat.ll
index e65148a..4236fab 100644
--- a/test/CodeGen/PowerPC/vaddsplat.ll
+++ b/test/CodeGen/PowerPC/vaddsplat.ll
@@ -16,7 +16,7 @@ define void @test_v4i32_pos_even(%v4i32* %P, %v4i32* %S) {
        ret void
 }
 
-; CHECK: test_v4i32_pos_even:
+; CHECK-LABEL: test_v4i32_pos_even:
 ; CHECK: vspltisw [[REG1:[0-9]+]], 9
 ; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG1]]
 
@@ -27,7 +27,7 @@ define void @test_v4i32_neg_even(%v4i32* %P, %v4i32* %S) {
        ret void
 }
 
-; CHECK: test_v4i32_neg_even:
+; CHECK-LABEL: test_v4i32_neg_even:
 ; CHECK: vspltisw [[REG1:[0-9]+]], -14
 ; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG1]]
 
@@ -38,7 +38,7 @@ define void @test_v8i16_pos_even(%v8i16* %P, %v8i16* %S) {
        ret void
 }
 
-; CHECK: test_v8i16_pos_even:
+; CHECK-LABEL: test_v8i16_pos_even:
 ; CHECK: vspltish [[REG1:[0-9]+]], 15
 ; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG1]]
 
@@ -49,7 +49,7 @@ define void @test_v8i16_neg_even(%v8i16* %P, %v8i16* %S) {
        ret void
 }
 
-; CHECK: test_v8i16_neg_even:
+; CHECK-LABEL: test_v8i16_neg_even:
 ; CHECK: vspltish [[REG1:[0-9]+]], -16
 ; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG1]]
 
@@ -60,7 +60,7 @@ define void @test_v16i8_pos_even(%v16i8* %P, %v16i8* %S) {
        ret void
 }
 
-; CHECK: test_v16i8_pos_even:
+; CHECK-LABEL: test_v16i8_pos_even:
 ; CHECK: vspltisb [[REG1:[0-9]+]], 8
 ; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG1]]
 
@@ -71,7 +71,7 @@ define void @test_v16i8_neg_even(%v16i8* %P, %v16i8* %S) {
        ret void
 }
 
-; CHECK: test_v16i8_neg_even:
+; CHECK-LABEL: test_v16i8_neg_even:
 ; CHECK: vspltisb [[REG1:[0-9]+]], -9
 ; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG1]]
 
@@ -82,7 +82,7 @@ define void @test_v4i32_pos_odd(%v4i32* %P, %v4i32* %S) {
        ret void
 }
 
-; CHECK: test_v4i32_pos_odd:
+; CHECK-LABEL: test_v4i32_pos_odd:
 ; CHECK: vspltisw [[REG2:[0-9]+]], -16
 ; CHECK: vspltisw [[REG1:[0-9]+]], 11
 ; CHECK: vsubuwm {{[0-9]+}}, [[REG1]], [[REG2]]
@@ -94,7 +94,7 @@ define void @test_v4i32_neg_odd(%v4i32* %P, %v4i32* %S) {
        ret void
 }
 
-; CHECK: test_v4i32_neg_odd:
+; CHECK-LABEL: test_v4i32_neg_odd:
 ; CHECK: vspltisw [[REG2:[0-9]+]], -16
 ; CHECK: vspltisw [[REG1:[0-9]+]], -11
 ; CHECK: vadduwm {{[0-9]+}}, [[REG1]], [[REG2]]
@@ -106,7 +106,7 @@ define void @test_v8i16_pos_odd(%v8i16* %P, %v8i16* %S) {
        ret void
 }
 
-; CHECK: test_v8i16_pos_odd:
+; CHECK-LABEL: test_v8i16_pos_odd:
 ; CHECK: vspltish [[REG2:[0-9]+]], -16
 ; CHECK: vspltish [[REG1:[0-9]+]], 15
 ; CHECK: vsubuhm {{[0-9]+}}, [[REG1]], [[REG2]]
@@ -118,7 +118,7 @@ define void @test_v8i16_neg_odd(%v8i16* %P, %v8i16* %S) {
        ret void
 }
 
-; CHECK: test_v8i16_neg_odd:
+; CHECK-LABEL: test_v8i16_neg_odd:
 ; CHECK: vspltish [[REG2:[0-9]+]], -16
 ; CHECK: vspltish [[REG1:[0-9]+]], -15
 ; CHECK: vadduhm {{[0-9]+}}, [[REG1]], [[REG2]]
@@ -130,7 +130,7 @@ define void @test_v16i8_pos_odd(%v16i8* %P, %v16i8* %S) {
        ret void
 }
 
-; CHECK: test_v16i8_pos_odd:
+; CHECK-LABEL: test_v16i8_pos_odd:
 ; CHECK: vspltisb [[REG2:[0-9]+]], -16
 ; CHECK: vspltisb [[REG1:[0-9]+]], 1
 ; CHECK: vsububm {{[0-9]+}}, [[REG1]], [[REG2]]
@@ -142,7 +142,7 @@ define void @test_v16i8_neg_odd(%v16i8* %P, %v16i8* %S) {
        ret void
 }
 
-; CHECK: test_v16i8_neg_odd:
+; CHECK-LABEL: test_v16i8_neg_odd:
 ; CHECK: vspltisb [[REG2:[0-9]+]], -16
 ; CHECK: vspltisb [[REG1:[0-9]+]], -1
 ; CHECK: vaddubm {{[0-9]+}}, [[REG1]], [[REG2]]
diff --git a/test/CodeGen/PowerPC/varargs.ll b/test/CodeGen/PowerPC/varargs.ll
index 90f0480..dfd2056 100644
--- a/test/CodeGen/PowerPC/varargs.ll
+++ b/test/CodeGen/PowerPC/varargs.ll
@@ -7,14 +7,14 @@ define i8* @test1(i8** %foo) nounwind {
   ret i8* %A
 }
 
-; P32: test1:
+; P32-LABEL: test1:
 ; P32: lwz r2, 0(r3)
 ; P32: addi r4, r2, 4
 ; P32: stw r4, 0(r3)
 ; P32: lwz r3, 0(r2)
 ; P32: blr 
 
-; P64: test1:
+; P64-LABEL: test1:
 ; P64: ld r2, 0(r3)
 ; P64: addi r4, r2, 8
 ; P64: std r4, 0(r3)
diff --git a/test/CodeGen/PowerPC/vec_constants.ll b/test/CodeGen/PowerPC/vec_constants.ll
index e4799e5..f16b9f5 100644
--- a/test/CodeGen/PowerPC/vec_constants.ll
+++ b/test/CodeGen/PowerPC/vec_constants.ll
@@ -17,14 +17,14 @@ define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind {
 	store <4 x float> %tmp13, <4 x float>* %P3
 	ret void
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK-NOT: CPI
 }
 
 define <4 x i32> @test_30() nounwind {
 	ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 >
 
-; CHECK: test_30:
+; CHECK-LABEL: test_30:
 ; CHECK: vspltisw
 ; CHECK-NEXT: vadduwm
 ; CHECK-NEXT: blr
@@ -33,7 +33,7 @@ define <4 x i32> @test_30() nounwind {
 define <4 x i32> @test_29() nounwind {
 	ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 >
 
-; CHECK: test_29:
+; CHECK-LABEL: test_29:
 ; CHECK: vspltisw
 ; CHECK-NEXT: vspltisw
 ; CHECK-NEXT: vsubuwm
@@ -43,7 +43,7 @@ define <4 x i32> @test_29() nounwind {
 define <8 x i16> @test_n30() nounwind {
 	ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 >
 
-; CHECK: test_n30:
+; CHECK-LABEL: test_n30:
 ; CHECK: vspltish
 ; CHECK-NEXT: vadduhm
 ; CHECK-NEXT: blr
@@ -52,7 +52,7 @@ define <8 x i16> @test_n30() nounwind {
 define <16 x i8> @test_n104() nounwind {
 	ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 >
 
-; CHECK: test_n104:
+; CHECK-LABEL: test_n104:
 ; CHECK: vspltisb
 ; CHECK-NEXT: vslb
 ; CHECK-NEXT: blr
@@ -61,7 +61,7 @@ define <16 x i8> @test_n104() nounwind {
 define <4 x i32> @test_vsldoi() nounwind {
 	ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 >
 
-; CHECK: test_vsldoi:
+; CHECK-LABEL: test_vsldoi:
 ; CHECK: vspltisw
 ; CHECK-NEXT: vsldoi
 ; CHECK-NEXT: blr
@@ -70,7 +70,7 @@ define <4 x i32> @test_vsldoi() nounwind {
 define <8 x i16> @test_vsldoi_65023() nounwind {
 	ret <8 x i16> < i16 65023, i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023 >
 
-; CHECK: test_vsldoi_65023:
+; CHECK-LABEL: test_vsldoi_65023:
 ; CHECK: vspltish
 ; CHECK-NEXT: vsldoi
 ; CHECK-NEXT: blr
@@ -79,7 +79,7 @@ define <8 x i16> @test_vsldoi_65023() nounwind {
 define <4 x i32> @test_rol() nounwind {
 	ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 >
 
-; CHECK: test_rol:
+; CHECK-LABEL: test_rol:
 ; CHECK: vspltisw
 ; CHECK-NEXT: vrlw
 ; CHECK-NEXT: blr
diff --git a/test/CodeGen/PowerPC/vec_mul.ll b/test/CodeGen/PowerPC/vec_mul.ll
index 53bc75d..c376751 100644
--- a/test/CodeGen/PowerPC/vec_mul.ll
+++ b/test/CodeGen/PowerPC/vec_mul.ll
@@ -6,7 +6,7 @@ define <4 x i32> @test_v4i32(<4 x i32>* %X, <4 x i32>* %Y) {
 	%tmp3 = mul <4 x i32> %tmp, %tmp2		; <<4 x i32>> [#uses=1]
 	ret <4 x i32> %tmp3
 }
-; CHECK: test_v4i32:
+; CHECK-LABEL: test_v4i32:
 ; CHECK: vmsumuhm
 ; CHECK-NOT: mullw
 
@@ -16,7 +16,7 @@ define <8 x i16> @test_v8i16(<8 x i16>* %X, <8 x i16>* %Y) {
 	%tmp3 = mul <8 x i16> %tmp, %tmp2		; <<8 x i16>> [#uses=1]
 	ret <8 x i16> %tmp3
 }
-; CHECK: test_v8i16:
+; CHECK-LABEL: test_v8i16:
 ; CHECK: vmladduhm
 ; CHECK-NOT: mullw
 
@@ -26,7 +26,7 @@ define <16 x i8> @test_v16i8(<16 x i8>* %X, <16 x i8>* %Y) {
 	%tmp3 = mul <16 x i8> %tmp, %tmp2		; <<16 x i8>> [#uses=1]
 	ret <16 x i8> %tmp3
 }
-; CHECK: test_v16i8:
+; CHECK-LABEL: test_v16i8:
 ; CHECK: vmuloub
 ; CHECK: vmuleub
 ; CHECK-NOT: mullw
@@ -40,7 +40,7 @@ define <4 x float> @test_float(<4 x float>* %X, <4 x float>* %Y) {
 ; Check the creation of a negative zero float vector by creating a vector of
 ; all bits set and shifting it 31 bits to left, resulting a an vector of 
 ; 4 x 0x80000000 (-0.0 as float).
-; CHECK: test_float:
+; CHECK-LABEL: test_float:
 ; CHECK: vspltisw [[ZNEG:[0-9]+]], -1
 ; CHECK: vslw     {{[0-9]+}}, [[ZNEG]], [[ZNEG]]
 ; CHECK: vmaddfp