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authorChris Lattner <sabre@nondot.org>2010-03-28 07:58:37 +0000
committerChris Lattner <sabre@nondot.org>2010-03-28 07:58:37 +0000
commitba47ce12443b57b786a245b9675af925b4710d61 (patch)
tree0f96e8a11fb6412fd4186987dd8498a9b8110de3 /test/CodeGen/PowerPC
parentcf3fed0fd4ac2e304120f7eef202ec87346d918c (diff)
downloadexternal_llvm-ba47ce12443b57b786a245b9675af925b4710d61.zip
external_llvm-ba47ce12443b57b786a245b9675af925b4710d61.tar.gz
external_llvm-ba47ce12443b57b786a245b9675af925b4710d61.tar.bz2
add some nounwinds
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99752 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/PowerPC')
-rw-r--r--test/CodeGen/PowerPC/eqv-andc-orc-nor.ll24
1 files changed, 12 insertions, 12 deletions
diff --git a/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll b/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll
index 558fd1b..f99089b 100644
--- a/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll
+++ b/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll
@@ -9,66 +9,66 @@
; RUN: llc < %s -march=ppc32 | \
; RUN: grep nand | count 1
-define i32 @EQV1(i32 %X, i32 %Y) {
+define i32 @EQV1(i32 %X, i32 %Y) nounwind {
%A = xor i32 %X, %Y ; <i32> [#uses=1]
%B = xor i32 %A, -1 ; <i32> [#uses=1]
ret i32 %B
}
-define i32 @EQV2(i32 %X, i32 %Y) {
+define i32 @EQV2(i32 %X, i32 %Y) nounwind {
%A = xor i32 %X, -1 ; <i32> [#uses=1]
%B = xor i32 %A, %Y ; <i32> [#uses=1]
ret i32 %B
}
-define i32 @EQV3(i32 %X, i32 %Y) {
+define i32 @EQV3(i32 %X, i32 %Y) nounwind {
%A = xor i32 %X, -1 ; <i32> [#uses=1]
%B = xor i32 %Y, %A ; <i32> [#uses=1]
ret i32 %B
}
-define i32 @ANDC1(i32 %X, i32 %Y) {
+define i32 @ANDC1(i32 %X, i32 %Y) nounwind {
%A = xor i32 %Y, -1 ; <i32> [#uses=1]
%B = and i32 %X, %A ; <i32> [#uses=1]
ret i32 %B
}
-define i32 @ANDC2(i32 %X, i32 %Y) {
+define i32 @ANDC2(i32 %X, i32 %Y) nounwind {
%A = xor i32 %X, -1 ; <i32> [#uses=1]
%B = and i32 %A, %Y ; <i32> [#uses=1]
ret i32 %B
}
-define i32 @ORC1(i32 %X, i32 %Y) {
+define i32 @ORC1(i32 %X, i32 %Y) nounwind {
%A = xor i32 %Y, -1 ; <i32> [#uses=1]
%B = or i32 %X, %A ; <i32> [#uses=1]
ret i32 %B
}
-define i32 @ORC2(i32 %X, i32 %Y) {
+define i32 @ORC2(i32 %X, i32 %Y) nounwind {
%A = xor i32 %X, -1 ; <i32> [#uses=1]
%B = or i32 %A, %Y ; <i32> [#uses=1]
ret i32 %B
}
-define i32 @NOR1(i32 %X) {
+define i32 @NOR1(i32 %X) nounwind {
%Y = xor i32 %X, -1 ; <i32> [#uses=1]
ret i32 %Y
}
-define i32 @NOR2(i32 %X, i32 %Y) {
+define i32 @NOR2(i32 %X, i32 %Y) nounwind {
%Z = or i32 %X, %Y ; <i32> [#uses=1]
%R = xor i32 %Z, -1 ; <i32> [#uses=1]
ret i32 %R
}
-define i32 @NAND1(i32 %X, i32 %Y) {
+define i32 @NAND1(i32 %X, i32 %Y) nounwind {
%Z = and i32 %X, %Y ; <i32> [#uses=1]
%W = xor i32 %Z, -1 ; <i32> [#uses=1]
ret i32 %W
}
-define void @VNOR(<4 x float>* %P, <4 x float>* %Q) {
+define void @VNOR(<4 x float>* %P, <4 x float>* %Q) nounwind {
%tmp = load <4 x float>* %P ; <<4 x float>> [#uses=1]
%tmp.upgrd.1 = bitcast <4 x float> %tmp to <4 x i32> ; <<4 x i32>> [#uses=1]
%tmp2 = load <4 x float>* %Q ; <<4 x float>> [#uses=1]
@@ -80,7 +80,7 @@ define void @VNOR(<4 x float>* %P, <4 x float>* %Q) {
ret void
}
-define void @VANDC(<4 x float>* %P, <4 x float>* %Q) {
+define void @VANDC(<4 x float>* %P, <4 x float>* %Q) nounwind {
%tmp = load <4 x float>* %P ; <<4 x float>> [#uses=1]
%tmp.upgrd.4 = bitcast <4 x float> %tmp to <4 x i32> ; <<4 x i32>> [#uses=1]
%tmp2 = load <4 x float>* %Q ; <<4 x float>> [#uses=1]