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author | Stephen Hines <srhines@google.com> | 2014-12-01 14:51:49 -0800 |
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committer | Stephen Hines <srhines@google.com> | 2014-12-02 16:08:10 -0800 |
commit | 37ed9c199ca639565f6ce88105f9e39e898d82d0 (patch) | |
tree | 8fb36d3910e3ee4c4e1b7422f4f017108efc52f5 /test/CodeGen/R600/add.ll | |
parent | d2327b22152ced7bc46dc629fc908959e8a52d03 (diff) | |
download | external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.zip external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.gz external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.bz2 |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
Diffstat (limited to 'test/CodeGen/R600/add.ll')
-rw-r--r-- | test/CodeGen/R600/add.ll | 96 |
1 files changed, 47 insertions, 49 deletions
diff --git a/test/CodeGen/R600/add.ll b/test/CodeGen/R600/add.ll index 711a2bc..767a642 100644 --- a/test/CodeGen/R600/add.ll +++ b/test/CodeGen/R600/add.ll @@ -1,12 +1,12 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK --check-prefix=FUNC %s ; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK --check-prefix=FUNC %s -;FUNC-LABEL: @test1: +;FUNC-LABEL: {{^}}test1: ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: V_ADD_I32_e32 [[REG:v[0-9]+]], {{v[0-9]+, v[0-9]+}} +;SI-CHECK: v_add_i32_e32 [[REG:v[0-9]+]], {{v[0-9]+, v[0-9]+}} ;SI-CHECK-NOT: [[REG]] -;SI-CHECK: BUFFER_STORE_DWORD [[REG]], +;SI-CHECK: buffer_store_dword [[REG]], define void @test1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { %b_ptr = getelementptr i32 addrspace(1)* %in, i32 1 %a = load i32 addrspace(1)* %in @@ -16,12 +16,12 @@ define void @test1(i32 addrspace(1)* %out, i32 addrspace(1)* %in) { ret void } -;FUNC-LABEL: @test2: +;FUNC-LABEL: {{^}}test2: ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <2 x i32> addrspace(1)* %in, i32 1 @@ -32,16 +32,16 @@ define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { ret void } -;FUNC-LABEL: @test4: +;FUNC-LABEL: {{^}}test4: ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;EG-CHECK: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} -;SI-CHECK: V_ADD_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} +;SI-CHECK: v_add_i32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { %b_ptr = getelementptr <4 x i32> addrspace(1)* %in, i32 1 @@ -52,7 +52,7 @@ define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { ret void } -; FUNC-LABEL: @test8 +; FUNC-LABEL: {{^}}test8: ; EG-CHECK: ADD_INT ; EG-CHECK: ADD_INT ; EG-CHECK: ADD_INT @@ -61,14 +61,14 @@ define void @test4(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %in) { ; EG-CHECK: ADD_INT ; EG-CHECK: ADD_INT ; EG-CHECK: ADD_INT -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 define void @test8(<8 x i32> addrspace(1)* %out, <8 x i32> %a, <8 x i32> %b) { entry: %0 = add <8 x i32> %a, %b @@ -76,7 +76,7 @@ entry: ret void } -; FUNC-LABEL: @test16 +; FUNC-LABEL: {{^}}test16: ; EG-CHECK: ADD_INT ; EG-CHECK: ADD_INT ; EG-CHECK: ADD_INT @@ -93,22 +93,22 @@ entry: ; EG-CHECK: ADD_INT ; EG-CHECK: ADD_INT ; EG-CHECK: ADD_INT -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADD_I32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 +; SI-CHECK: s_add_i32 define void @test16(<16 x i32> addrspace(1)* %out, <16 x i32> %a, <16 x i32> %b) { entry: %0 = add <16 x i32> %a, %b @@ -116,9 +116,9 @@ entry: ret void } -; FUNC-LABEL: @add64 -; SI-CHECK: S_ADD_I32 -; SI-CHECK: S_ADDC_U32 +; FUNC-LABEL: {{^}}add64: +; SI-CHECK: s_add_u32 +; SI-CHECK: s_addc_u32 define void @add64(i64 addrspace(1)* %out, i64 %a, i64 %b) { entry: %0 = add i64 %a, %b @@ -126,13 +126,13 @@ entry: ret void } -; The V_ADDC_U32 and V_ADD_I32 instruction can't read SGPRs, because they +; The v_addc_u32 and v_add_i32 instruction can't read SGPRs, because they ; use VCC. The test is designed so that %a will be stored in an SGPR and ; %0 will be stored in a VGPR, so the comiler will be forced to copy %a ; to a VGPR before doing the add. -; FUNC-LABEL: @add64_sgpr_vgpr -; SI-CHECK-NOT: V_ADDC_U32_e32 s +; FUNC-LABEL: {{^}}add64_sgpr_vgpr: +; SI-CHECK-NOT: v_addc_u32_e32 s define void @add64_sgpr_vgpr(i64 addrspace(1)* %out, i64 %a, i64 addrspace(1)* %in) { entry: %0 = load i64 addrspace(1)* %in @@ -141,12 +141,10 @@ entry: ret void } -; Test i64 add inside a branch. We don't allow SALU instructions inside of -; branches. -; FIXME: We are being conservative here. We could allow this in some cases. -; FUNC-LABEL: @add64_in_branch -; SI-CHECK-NOT: S_ADD_I32 -; SI-CHECK-NOT: S_ADDC_U32 +; Test i64 add inside a branch. +; FUNC-LABEL: {{^}}add64_in_branch: +; SI-CHECK: s_add_u32 +; SI-CHECK: s_addc_u32 define void @add64_in_branch(i64 addrspace(1)* %out, i64 addrspace(1)* %in, i64 %a, i64 %b, i64 %c) { entry: %0 = icmp eq i64 %a, 0 |