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author | Stephen Hines <srhines@google.com> | 2014-12-01 14:51:49 -0800 |
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committer | Stephen Hines <srhines@google.com> | 2014-12-02 16:08:10 -0800 |
commit | 37ed9c199ca639565f6ce88105f9e39e898d82d0 (patch) | |
tree | 8fb36d3910e3ee4c4e1b7422f4f017108efc52f5 /test/CodeGen/R600/build_vector.ll | |
parent | d2327b22152ced7bc46dc629fc908959e8a52d03 (diff) | |
download | external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.zip external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.gz external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.bz2 |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
Diffstat (limited to 'test/CodeGen/R600/build_vector.ll')
-rw-r--r-- | test/CodeGen/R600/build_vector.ll | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/test/CodeGen/R600/build_vector.ll b/test/CodeGen/R600/build_vector.ll index 8179de1..9137eee 100644 --- a/test/CodeGen/R600/build_vector.ll +++ b/test/CodeGen/R600/build_vector.ll @@ -1,32 +1,32 @@ ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK ; RUN: llc < %s -march=r600 -mcpu=SI -verify-machineinstrs | FileCheck %s --check-prefix=SI-CHECK -; R600-CHECK: @build_vector2 +; R600-CHECK: {{^}}build_vector2: ; R600-CHECK: MOV ; R600-CHECK: MOV ; R600-CHECK-NOT: MOV -; SI-CHECK: @build_vector2 -; SI-CHECK-DAG: V_MOV_B32_e32 v[[X:[0-9]]], 5 -; SI-CHECK-DAG: V_MOV_B32_e32 v[[Y:[0-9]]], 6 -; SI-CHECK: BUFFER_STORE_DWORDX2 v{{\[}}[[X]]:[[Y]]{{\]}} +; SI-CHECK: {{^}}build_vector2: +; SI-CHECK-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5 +; SI-CHECK-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6 +; SI-CHECK: buffer_store_dwordx2 v{{\[}}[[X]]:[[Y]]{{\]}} define void @build_vector2 (<2 x i32> addrspace(1)* %out) { entry: store <2 x i32> <i32 5, i32 6>, <2 x i32> addrspace(1)* %out ret void } -; R600-CHECK: @build_vector4 +; R600-CHECK: {{^}}build_vector4: ; R600-CHECK: MOV ; R600-CHECK: MOV ; R600-CHECK: MOV ; R600-CHECK: MOV ; R600-CHECK-NOT: MOV -; SI-CHECK: @build_vector4 -; SI-CHECK-DAG: V_MOV_B32_e32 v[[X:[0-9]]], 5 -; SI-CHECK-DAG: V_MOV_B32_e32 v[[Y:[0-9]]], 6 -; SI-CHECK-DAG: V_MOV_B32_e32 v[[Z:[0-9]]], 7 -; SI-CHECK-DAG: V_MOV_B32_e32 v[[W:[0-9]]], 8 -; SI-CHECK: BUFFER_STORE_DWORDX4 v{{\[}}[[X]]:[[W]]{{\]}} +; SI-CHECK: {{^}}build_vector4: +; SI-CHECK-DAG: v_mov_b32_e32 v[[X:[0-9]]], 5 +; SI-CHECK-DAG: v_mov_b32_e32 v[[Y:[0-9]]], 6 +; SI-CHECK-DAG: v_mov_b32_e32 v[[Z:[0-9]]], 7 +; SI-CHECK-DAG: v_mov_b32_e32 v[[W:[0-9]]], 8 +; SI-CHECK: buffer_store_dwordx4 v{{\[}}[[X]]:[[W]]{{\]}} define void @build_vector4 (<4 x i32> addrspace(1)* %out) { entry: store <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> addrspace(1)* %out |