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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-07-31 20:43:27 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-07-31 20:43:27 +0000 |
| commit | 6b3f6a744a6d16c5d62dc3477186035e8a74a8e9 (patch) | |
| tree | 1ace9471553c04326bc676bbc6b2cea18352a250 /test/CodeGen/R600/fadd.ll | |
| parent | 5519dc9de88b36a2250db0faaf78c55f5e2c4d00 (diff) | |
| download | external_llvm-6b3f6a744a6d16c5d62dc3477186035e8a74a8e9.zip external_llvm-6b3f6a744a6d16c5d62dc3477186035e8a74a8e9.tar.gz external_llvm-6b3f6a744a6d16c5d62dc3477186035e8a74a8e9.tar.bz2 | |
Revert "R600: Non vector only instruction can be scheduled on trans unit"
This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187526 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/R600/fadd.ll')
| -rw-r--r-- | test/CodeGen/R600/fadd.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/CodeGen/R600/fadd.ll b/test/CodeGen/R600/fadd.ll index 205715d..9a67232 100644 --- a/test/CodeGen/R600/fadd.ll +++ b/test/CodeGen/R600/fadd.ll @@ -18,7 +18,7 @@ declare void @llvm.AMDGPU.store.output(float, i32) ; CHECK: @fadd_v4f32 ; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -; CHECK: ADD T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} define void @fadd_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { |