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| author | Stephen Hines <srhines@google.com> | 2014-12-01 14:51:49 -0800 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-12-02 16:08:10 -0800 |
| commit | 37ed9c199ca639565f6ce88105f9e39e898d82d0 (patch) | |
| tree | 8fb36d3910e3ee4c4e1b7422f4f017108efc52f5 /test/CodeGen/R600/fceil.ll | |
| parent | d2327b22152ced7bc46dc629fc908959e8a52d03 (diff) | |
| download | external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.zip external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.gz external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.bz2 | |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
Diffstat (limited to 'test/CodeGen/R600/fceil.ll')
| -rw-r--r-- | test/CodeGen/R600/fceil.ll | 80 |
1 files changed, 40 insertions, 40 deletions
diff --git a/test/CodeGen/R600/fceil.ll b/test/CodeGen/R600/fceil.ll index 458363a..56dc796 100644 --- a/test/CodeGen/R600/fceil.ll +++ b/test/CodeGen/R600/fceil.ll @@ -8,8 +8,8 @@ declare <4 x float> @llvm.ceil.v4f32(<4 x float>) nounwind readnone declare <8 x float> @llvm.ceil.v8f32(<8 x float>) nounwind readnone declare <16 x float> @llvm.ceil.v16f32(<16 x float>) nounwind readnone -; FUNC-LABEL: @fceil_f32: -; SI: V_CEIL_F32_e32 +; FUNC-LABEL: {{^}}fceil_f32: +; SI: v_ceil_f32_e32 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+\.[XYZW]]] ; EG: CEIL {{\*? *}}[[RESULT]] define void @fceil_f32(float addrspace(1)* %out, float %x) { @@ -18,9 +18,9 @@ define void @fceil_f32(float addrspace(1)* %out, float %x) { ret void } -; FUNC-LABEL: @fceil_v2f32: -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 +; FUNC-LABEL: {{^}}fceil_v2f32: +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}} ; EG: CEIL {{\*? *}}[[RESULT]] ; EG: CEIL {{\*? *}}[[RESULT]] @@ -30,10 +30,10 @@ define void @fceil_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %x) { ret void } -; FUNC-LABEL: @fceil_v3f32: -; FIXME-SI: V_CEIL_F32_e32 -; FIXME-SI: V_CEIL_F32_e32 -; FIXME-SI: V_CEIL_F32_e32 +; FUNC-LABEL: {{^}}fceil_v3f32: +; FIXME-SI: v_ceil_f32_e32 +; FIXME-SI: v_ceil_f32_e32 +; FIXME-SI: v_ceil_f32_e32 ; FIXME-EG: v3 is treated as v2 and v1, hence 2 stores ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}} ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}} @@ -46,11 +46,11 @@ define void @fceil_v3f32(<3 x float> addrspace(1)* %out, <3 x float> %x) { ret void } -; FUNC-LABEL: @fceil_v4f32: -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 +; FUNC-LABEL: {{^}}fceil_v4f32: +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT:T[0-9]+]]{{\.[XYZW]}} ; EG: CEIL {{\*? *}}[[RESULT]] ; EG: CEIL {{\*? *}}[[RESULT]] @@ -62,15 +62,15 @@ define void @fceil_v4f32(<4 x float> addrspace(1)* %out, <4 x float> %x) { ret void } -; FUNC-LABEL: @fceil_v8f32: -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 +; FUNC-LABEL: {{^}}fceil_v8f32: +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}} ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}} ; EG-DAG: CEIL {{\*? *}}[[RESULT1]] @@ -87,23 +87,23 @@ define void @fceil_v8f32(<8 x float> addrspace(1)* %out, <8 x float> %x) { ret void } -; FUNC-LABEL: @fceil_v16f32: -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 -; SI: V_CEIL_F32_e32 +; FUNC-LABEL: {{^}}fceil_v16f32: +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 +; SI: v_ceil_f32_e32 ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT1:T[0-9]+]]{{\.[XYZW]}} ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT2:T[0-9]+]]{{\.[XYZW]}} ; EG: MEM_RAT_CACHELESS STORE_RAW [[RESULT3:T[0-9]+]]{{\.[XYZW]}} |