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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-10-10 17:11:24 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-10-10 17:11:24 +0000 |
| commit | 0f9eaaa8aa10bdb658e887782b86f03dbea79cb1 (patch) | |
| tree | 1b06eb716b8934bcfcc7f104657cc3db65e3e5ab /test/CodeGen/R600/fconst64.ll | |
| parent | 219e788dc6e38120266d366a51286739fa33123b (diff) | |
| download | external_llvm-0f9eaaa8aa10bdb658e887782b86f03dbea79cb1.zip external_llvm-0f9eaaa8aa10bdb658e887782b86f03dbea79cb1.tar.gz external_llvm-0f9eaaa8aa10bdb658e887782b86f03dbea79cb1.tar.bz2 | |
R600/SI: Define a separate MIMG instruction for each possible output value type
During instruction selection, we rewrite the destination register
class for MIMG instructions based on their writemasks. This creates
machine verifier errors since the new register class does not match
the register class in the MIMG instruction definition.
We can avoid this by defining different MIMG instructions for each
possible destination type and then switching to the correct instruction
when we change the register class.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192365 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/R600/fconst64.ll')
0 files changed, 0 insertions, 0 deletions