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authorTom Stellard <thomas.stellard@amd.com>2013-07-31 20:43:27 +0000
committerTom Stellard <thomas.stellard@amd.com>2013-07-31 20:43:27 +0000
commit6b3f6a744a6d16c5d62dc3477186035e8a74a8e9 (patch)
tree1ace9471553c04326bc676bbc6b2cea18352a250 /test/CodeGen/R600/fp_to_sint.ll
parent5519dc9de88b36a2250db0faaf78c55f5e2c4d00 (diff)
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Revert "R600: Non vector only instruction can be scheduled on trans unit"
This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187526 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/R600/fp_to_sint.ll')
-rw-r--r--test/CodeGen/R600/fp_to_sint.ll6
1 files changed, 3 insertions, 3 deletions
diff --git a/test/CodeGen/R600/fp_to_sint.ll b/test/CodeGen/R600/fp_to_sint.ll
index c051631..7b430e3 100644
--- a/test/CodeGen/R600/fp_to_sint.ll
+++ b/test/CodeGen/R600/fp_to_sint.ll
@@ -2,9 +2,9 @@
; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK
; R600-CHECK: @fp_to_sint_v4i32
-; R600-CHECK: FLT_TO_INT * T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
-; R600-CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW]}}
-; R600-CHECK: FLT_TO_INT T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+; R600-CHECK: FLT_TO_INT {{[* ]*}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+; R600-CHECK: FLT_TO_INT {{[* ]*}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
+; R600-CHECK: FLT_TO_INT {{[* ]*}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
; R600-CHECK: FLT_TO_INT {{[* ]*}}T{{[0-9]+\.[XYZW], PV\.[XYZW]}}
; SI-CHECK: @fp_to_sint_v4i32
; SI-CHECK: V_CVT_I32_F32_e32