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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-16 23:51:24 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-16 23:51:24 +0000 |
| commit | 0991c314d7c1a2052963dc89af1d2f07134488b6 (patch) | |
| tree | 7d4b9cd9f16d7b430df1947a238e6e3c3cc7f0cf /test/CodeGen/R600/fsub.ll | |
| parent | 62c7749437a74a4e0cf28edff865bd82f2b9aecc (diff) | |
| download | external_llvm-0991c314d7c1a2052963dc89af1d2f07134488b6.zip external_llvm-0991c314d7c1a2052963dc89af1d2f07134488b6.tar.gz external_llvm-0991c314d7c1a2052963dc89af1d2f07134488b6.tar.bz2 | |
R600: Expand vector float operations for both SI and R600
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188596 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/R600/fsub.ll')
| -rw-r--r-- | test/CodeGen/R600/fsub.ll | 45 |
1 files changed, 27 insertions, 18 deletions
diff --git a/test/CodeGen/R600/fsub.ll b/test/CodeGen/R600/fsub.ll index b45aaff..1608c3a 100644 --- a/test/CodeGen/R600/fsub.ll +++ b/test/CodeGen/R600/fsub.ll @@ -1,23 +1,27 @@ -; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600-CHECK +; RUN: llc < %s -march=r600 -mcpu=SI | FileCheck %s --check-prefix=SI-CHECK -; CHECK: @fsub_f32 -; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} - -define void @fsub_f32() { - %r0 = call float @llvm.R600.load.input(i32 0) - %r1 = call float @llvm.R600.load.input(i32 1) - %r2 = fsub float %r0, %r1 - call void @llvm.AMDGPU.store.output(float %r2, i32 0) - ret void +; R600-CHECK: @fsub_f32 +; R600-CHECK: ADD * T{{[0-9]+\.[XYZW]}}, KC0[2].Z, -KC0[2].W +; SI-CHECK: @fsub_f32 +; SI-CHECK: V_SUB_F32 +define void @fsub_f32(float addrspace(1)* %out, float %a, float %b) { +entry: + %0 = fsub float %a, %b + store float %0, float addrspace(1)* %out + ret void } declare float @llvm.R600.load.input(i32) readnone declare void @llvm.AMDGPU.store.output(float, i32) -; CHECK: @fsub_v2f32 -; CHECK-DAG: ADD * T{{[0-9]+\.[XYZW]}}, KC0[3].X, -KC0[3].Z -; CHECK-DAG: ADD * T{{[0-9]+\.[XYZW]}}, KC0[2].W, -KC0[3].Y +; R600-CHECK: @fsub_v2f32 +; R600-CHECK-DAG: ADD * T{{[0-9]+\.[XYZW]}}, KC0[3].X, -KC0[3].Z +; R600-CHECK-DAG: ADD * T{{[0-9]+\.[XYZW]}}, KC0[2].W, -KC0[3].Y +; SI-CHECK: @fsub_v2f32 +; SI-CHECK: V_SUB_F32 +; SI-CHECK: V_SUB_F32 define void @fsub_v2f32(<2 x float> addrspace(1)* %out, <2 x float> %a, <2 x float> %b) { entry: %0 = fsub <2 x float> %a, %b @@ -25,11 +29,16 @@ entry: ret void } -; CHECK: @fsub_v4f32 -; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} -; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} -; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} -; CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} +; R600-CHECK: @fsub_v4f32 +; R600-CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} +; R600-CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} +; R600-CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} +; R600-CHECK: ADD * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], -T[0-9]+\.[XYZW]}} +; SI-CHECK: @fsub_v4f32 +; SI-CHECK: V_SUB_F32 +; SI-CHECK: V_SUB_F32 +; SI-CHECK: V_SUB_F32 +; SI-CHECK: V_SUB_F32 define void @fsub_v4f32(<4 x float> addrspace(1)* %out, <4 x float> addrspace(1)* %in) { %b_ptr = getelementptr <4 x float> addrspace(1)* %in, i32 1 %a = load <4 x float> addrspace(1) * %in |