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| author | Stephen Hines <srhines@google.com> | 2014-12-01 14:51:49 -0800 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-12-02 16:08:10 -0800 |
| commit | 37ed9c199ca639565f6ce88105f9e39e898d82d0 (patch) | |
| tree | 8fb36d3910e3ee4c4e1b7422f4f017108efc52f5 /test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll | |
| parent | d2327b22152ced7bc46dc629fc908959e8a52d03 (diff) | |
| download | external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.zip external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.gz external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.bz2 | |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
Diffstat (limited to 'test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll')
| -rw-r--r-- | test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll b/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll index c8c7357..009fd73 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.div_fixup.ll @@ -3,23 +3,23 @@ declare float @llvm.AMDGPU.div.fixup.f32(float, float, float) nounwind readnone declare double @llvm.AMDGPU.div.fixup.f64(double, double, double) nounwind readnone -; SI-LABEL: @test_div_fixup_f32: -; SI-DAG: S_LOAD_DWORD [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb -; SI-DAG: S_LOAD_DWORD [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd -; SI-DAG: V_MOV_B32_e32 [[VC:v[0-9]+]], [[SC]] -; SI-DAG: S_LOAD_DWORD [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc -; SI: V_MOV_B32_e32 [[VB:v[0-9]+]], [[SB]] -; SI: V_DIV_FIXUP_F32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]] -; SI: BUFFER_STORE_DWORD [[RESULT]], -; SI: S_ENDPGM +; SI-LABEL: {{^}}test_div_fixup_f32: +; SI-DAG: s_load_dword [[SA:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xb +; SI-DAG: s_load_dword [[SC:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xd +; SI-DAG: s_load_dword [[SB:s[0-9]+]], s{{\[[0-9]+:[0-9]+\]}}, 0xc +; SI-DAG: v_mov_b32_e32 [[VC:v[0-9]+]], [[SC]] +; SI-DAG: v_mov_b32_e32 [[VB:v[0-9]+]], [[SB]] +; SI: v_div_fixup_f32 [[RESULT:v[0-9]+]], [[SA]], [[VB]], [[VC]] +; SI: buffer_store_dword [[RESULT]], +; SI: s_endpgm define void @test_div_fixup_f32(float addrspace(1)* %out, float %a, float %b, float %c) nounwind { %result = call float @llvm.AMDGPU.div.fixup.f32(float %a, float %b, float %c) nounwind readnone store float %result, float addrspace(1)* %out, align 4 ret void } -; SI-LABEL: @test_div_fixup_f64: -; SI: V_DIV_FIXUP_F64 +; SI-LABEL: {{^}}test_div_fixup_f64: +; SI: v_div_fixup_f64 define void @test_div_fixup_f64(double addrspace(1)* %out, double %a, double %b, double %c) nounwind { %result = call double @llvm.AMDGPU.div.fixup.f64(double %a, double %b, double %c) nounwind readnone store double %result, double addrspace(1)* %out, align 8 |