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author | Stephen Hines <srhines@google.com> | 2014-04-23 16:57:46 -0700 |
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committer | Stephen Hines <srhines@google.com> | 2014-04-24 15:53:16 -0700 |
commit | 36b56886974eae4f9c5ebc96befd3e7bfe5de338 (patch) | |
tree | e6cfb69fbbd937f450eeb83bfb83b9da3b01275a /test/CodeGen/R600/llvm.AMDGPU.umax.ll | |
parent | 69a8640022b04415ae9fac62f8ab090601d8f889 (diff) | |
download | external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.zip external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.tar.gz external_llvm-36b56886974eae4f9c5ebc96befd3e7bfe5de338.tar.bz2 |
Update to LLVM 3.5a.
Change-Id: Ifadecab779f128e62e430c2b4f6ddd84953ed617
Diffstat (limited to 'test/CodeGen/R600/llvm.AMDGPU.umax.ll')
-rw-r--r-- | test/CodeGen/R600/llvm.AMDGPU.umax.ll | 44 |
1 files changed, 35 insertions, 9 deletions
diff --git a/test/CodeGen/R600/llvm.AMDGPU.umax.ll b/test/CodeGen/R600/llvm.AMDGPU.umax.ll index 4cfa133..1b8da2e 100644 --- a/test/CodeGen/R600/llvm.AMDGPU.umax.ll +++ b/test/CodeGen/R600/llvm.AMDGPU.umax.ll @@ -1,12 +1,38 @@ -;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck %s +; RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck -check-prefix=SI %s -;CHECK: V_MAX_U32_e32 - -define void @main(i32 %p0, i32 %p1) #0 { +; SI-LABEL: @vector_umax +; SI: V_MAX_U32_e32 +define void @vector_umax(i32 %p0, i32 %p1, i32 addrspace(1)* %in) #0 { main_body: - %0 = call i32 @llvm.AMDGPU.umax(i32 %p0, i32 %p1) - %1 = bitcast i32 %0 to float - call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %1, float %1, float %1, float %1) + %load = load i32 addrspace(1)* %in, align 4 + %max = call i32 @llvm.AMDGPU.umax(i32 %p0, i32 %load) + %bc = bitcast i32 %max to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc) + ret void +} + +; SI-LABEL: @scalar_umax +; SI: S_MAX_U32 +define void @scalar_umax(i32 %p0, i32 %p1) #0 { +entry: + %max = call i32 @llvm.AMDGPU.umax(i32 %p0, i32 %p1) + %bc = bitcast i32 %max to float + call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 0, float %bc, float %bc, float %bc, float %bc) + ret void +} + +; SI-LABEL: @trunc_zext_umax +; SI: BUFFER_LOAD_UBYTE [[VREG:v[0-9]+]], +; SI: V_MAX_U32_e32 [[RESULT:v[0-9]+]], 0, [[VREG]] +; SI-NOT: AND +; SI: BUFFER_STORE_SHORT [[RESULT]], +define void @trunc_zext_umax(i16 addrspace(1)* nocapture %out, i8 addrspace(1)* nocapture %src) nounwind { + %tmp5 = load i8 addrspace(1)* %src, align 1 + %tmp2 = zext i8 %tmp5 to i32 + %tmp3 = tail call i32 @llvm.AMDGPU.umax(i32 %tmp2, i32 0) nounwind readnone + %tmp4 = trunc i32 %tmp3 to i8 + %tmp6 = zext i8 %tmp4 to i16 + store i16 %tmp6, i16 addrspace(1)* %out, align 2 ret void } @@ -15,7 +41,7 @@ declare i32 @llvm.AMDGPU.umax(i32, i32) #1 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) -attributes #0 = { "ShaderType"="0" } -attributes #1 = { readnone } +attributes #0 = { nounwind } +attributes #1 = { nounwind readnone } !0 = metadata !{metadata !"const", null, i32 1} |