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authorTom Stellard <thomas.stellard@amd.com>2013-08-16 01:11:46 +0000
committerTom Stellard <thomas.stellard@amd.com>2013-08-16 01:11:46 +0000
commite560d526a1aebf45e5333ab7b24689be930a8026 (patch)
tree5ba5f513f854c36d3606b30655c4f482b7512a96 /test/CodeGen/R600/load.ll
parent24ec2e5a72d7fca58f8ae2b3c01501a9927ef04e (diff)
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R600: Change the RAT instruction assembly names so they match the docs
Tested-by: Aaron Watry <awatry@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188515 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/R600/load.ll')
-rw-r--r--test/CodeGen/R600/load.ll12
1 files changed, 6 insertions, 6 deletions
diff --git a/test/CodeGen/R600/load.ll b/test/CodeGen/R600/load.ll
index f478ef5..22aed6a 100644
--- a/test/CodeGen/R600/load.ll
+++ b/test/CodeGen/R600/load.ll
@@ -104,8 +104,8 @@ entry:
}
; R600-CHECK: @load_i64
-; R600-CHECK: RAT
-; R600-CHECK: RAT
+; R600-CHECK: MEM_RAT
+; R600-CHECK: MEM_RAT
; SI-CHECK: @load_i64
; SI-CHECK: BUFFER_LOAD_DWORDX2
@@ -117,8 +117,8 @@ entry:
}
; R600-CHECK: @load_i64_sext
-; R600-CHECK: RAT
-; R600-CHECK: RAT
+; R600-CHECK: MEM_RAT
+; R600-CHECK: MEM_RAT
; R600-CHECK: ASHR {{[* ]*}}T{{[0-9]\.[XYZW]}}, T{{[0-9]\.[XYZW]}}, literal.x
; R600-CHECK: 31
; SI-CHECK: @load_i64_sext
@@ -135,8 +135,8 @@ entry:
}
; R600-CHECK: @load_i64_zext
-; R600-CHECK: RAT
-; R600-CHECK: RAT
+; R600-CHECK: MEM_RAT
+; R600-CHECK: MEM_RAT
define void @load_i64_zext(i64 addrspace(1)* %out, i32 addrspace(1)* %in) {
entry:
%0 = load i32 addrspace(1)* %in