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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-01 15:23:42 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-01 15:23:42 +0000 |
| commit | 692ee102ebef535d311c35d53457028083e5c5be (patch) | |
| tree | 5966632bb87e4120a27dadfce4187535429a4275 /test/CodeGen/R600/load.vec.ll | |
| parent | 98b357e1cd0d41108e6011725dad6a6dbf208a38 (diff) | |
| download | external_llvm-692ee102ebef535d311c35d53457028083e5c5be.zip external_llvm-692ee102ebef535d311c35d53457028083e5c5be.tar.gz external_llvm-692ee102ebef535d311c35d53457028083e5c5be.tar.bz2 | |
R600: Add 64-bit float load/store support
* Added R600_Reg64 class
* Added T#Index#.XY registers definition
* Added v2i32 register reads from parameter and global space
* Added f32 and i32 elements extraction from v2f32 and v2i32
* Added v2i32 -> v2f32 conversions
Tom Stellard:
- Mark vec2 operations as expand. The addition of a vec2 register
class made them all legal.
Patch by: Dmitry Cherkassov
Signed-off-by: Dmitry Cherkassov <dcherkassov@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187582 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/R600/load.vec.ll')
| -rw-r--r-- | test/CodeGen/R600/load.vec.ll | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/test/CodeGen/R600/load.vec.ll b/test/CodeGen/R600/load.vec.ll index b3d6349..8cba0b6 100644 --- a/test/CodeGen/R600/load.vec.ll +++ b/test/CodeGen/R600/load.vec.ll @@ -3,8 +3,7 @@ ; load a v2i32 value from the global address space. ; EG-CHECK: @load_v2i32 -; EG-CHECK-DAG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 4 -; EG-CHECK-DAG: VTX_READ_32 T{{[0-9]+}}.X, T{{[0-9]+}}.X, 0 +; EG-CHECK: VTX_READ_64 T{{[0-9]+}}.XY, T{{[0-9]+}}.X, 0 ; SI-CHECK: @load_v2i32 ; SI-CHECK: BUFFER_LOAD_DWORDX2 VGPR{{[0-9]+}} define void @load_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { |