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| author | Stephen Hines <srhines@google.com> | 2014-12-01 14:51:49 -0800 |
|---|---|---|
| committer | Stephen Hines <srhines@google.com> | 2014-12-02 16:08:10 -0800 |
| commit | 37ed9c199ca639565f6ce88105f9e39e898d82d0 (patch) | |
| tree | 8fb36d3910e3ee4c4e1b7422f4f017108efc52f5 /test/CodeGen/R600/rotl.ll | |
| parent | d2327b22152ced7bc46dc629fc908959e8a52d03 (diff) | |
| download | external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.zip external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.gz external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.bz2 | |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
Diffstat (limited to 'test/CodeGen/R600/rotl.ll')
| -rw-r--r-- | test/CodeGen/R600/rotl.ll | 38 |
1 files changed, 20 insertions, 18 deletions
diff --git a/test/CodeGen/R600/rotl.ll b/test/CodeGen/R600/rotl.ll index 83f657f..6c8e503 100644 --- a/test/CodeGen/R600/rotl.ll +++ b/test/CodeGen/R600/rotl.ll @@ -1,14 +1,14 @@ ; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck --check-prefix=R600 -check-prefix=FUNC %s ; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s -; FUNC-LABEL: @rotl_i32: +; FUNC-LABEL: {{^}}rotl_i32: ; R600: SUB_INT {{\** T[0-9]+\.[XYZW]}}, literal.x ; R600-NEXT: 32 ; R600: BIT_ALIGN_INT {{T[0-9]+\.[XYZW]}}, KC0[2].Z, KC0[2].Z, PV.{{[XYZW]}} -; SI: S_SUB_I32 [[SDST:s[0-9]+]], 32, {{[s][0-9]+}} -; SI: V_MOV_B32_e32 [[VDST:v[0-9]+]], [[SDST]] -; SI: V_ALIGNBIT_B32 {{v[0-9]+, [s][0-9]+, v[0-9]+}}, [[VDST]] +; SI: s_sub_i32 [[SDST:s[0-9]+]], 32, {{[s][0-9]+}} +; SI: v_mov_b32_e32 [[VDST:v[0-9]+]], [[SDST]] +; SI: v_alignbit_b32 {{v[0-9]+, [s][0-9]+, s[0-9]+}}, [[VDST]] define void @rotl_i32(i32 addrspace(1)* %in, i32 %x, i32 %y) { entry: %0 = shl i32 %x, %y @@ -19,11 +19,12 @@ entry: ret void } -; FUNC-LABEL: @rotl_v2i32 -; SI: S_SUB_I32 -; SI: V_ALIGNBIT_B32 -; SI: S_SUB_I32 -; SI: V_ALIGNBIT_B32 +; FUNC-LABEL: {{^}}rotl_v2i32: +; SI-DAG: s_sub_i32 +; SI-DAG: s_sub_i32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: v_alignbit_b32 +; SI: s_endpgm define void @rotl_v2i32(<2 x i32> addrspace(1)* %in, <2 x i32> %x, <2 x i32> %y) { entry: %0 = shl <2 x i32> %x, %y @@ -34,15 +35,16 @@ entry: ret void } -; FUNC-LABEL: @rotl_v4i32 -; SI: S_SUB_I32 -; SI: V_ALIGNBIT_B32 -; SI: S_SUB_I32 -; SI: V_ALIGNBIT_B32 -; SI: S_SUB_I32 -; SI: V_ALIGNBIT_B32 -; SI: S_SUB_I32 -; SI: V_ALIGNBIT_B32 +; FUNC-LABEL: {{^}}rotl_v4i32: +; SI-DAG: s_sub_i32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: s_sub_i32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: s_sub_i32 +; SI-DAG: v_alignbit_b32 +; SI-DAG: s_sub_i32 +; SI-DAG: v_alignbit_b32 +; SI: s_endpgm define void @rotl_v4i32(<4 x i32> addrspace(1)* %in, <4 x i32> %x, <4 x i32> %y) { entry: %0 = shl <4 x i32> %x, %y |