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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-11-13 23:36:37 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-11-13 23:36:37 +0000 |
| commit | b52bf6a3b31596a309f4b12884522e9b4a344654 (patch) | |
| tree | 60294ecd3670543e55b24aca1a4507c391649203 /test/CodeGen/R600/sra.ll | |
| parent | eef8b8c35c585d941fb14c66df3cebc46b33f776 (diff) | |
| download | external_llvm-b52bf6a3b31596a309f4b12884522e9b4a344654.zip external_llvm-b52bf6a3b31596a309f4b12884522e9b4a344654.tar.gz external_llvm-b52bf6a3b31596a309f4b12884522e9b4a344654.tar.bz2 | |
R600/SI: Prefer SALU instructions for bit shift operations
All shift operations will be selected as SALU instructions and then
if necessary lowered to VALU instructions in the SIFixSGPRCopies pass.
This allows us to do more operations on the SALU which will improve
performance and is also required for implementing private memory
using indirect addressing, since the private memory pointers must stay
in the scalar registers.
This patch includes some fixes from Matt Arsenault.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194625 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/R600/sra.ll')
| -rw-r--r-- | test/CodeGen/R600/sra.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/CodeGen/R600/sra.ll b/test/CodeGen/R600/sra.ll index 2190b3c..2926163 100644 --- a/test/CodeGen/R600/sra.ll +++ b/test/CodeGen/R600/sra.ll @@ -1,11 +1,11 @@ ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG-CHECK %s ;RUN: llc < %s -march=r600 -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=SI-CHECK %s -;EG-CHECK: @ashr_v2i32 +;EG-CHECK-LABEL: @ashr_v2i32 ;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: @ashr_v2i32 +;SI-CHECK-LABEL: @ashr_v2i32 ;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} ;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} @@ -18,13 +18,13 @@ define void @ashr_v2i32(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %i ret void } -;EG-CHECK: @ashr_v4i32 +;EG-CHECK-LABEL: @ashr_v4i32 ;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;EG-CHECK: ASHR {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;SI-CHECK: @ashr_v4i32 +;SI-CHECK-LABEL: @ashr_v4i32 ;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} ;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} ;SI-CHECK: V_ASHR_I32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}} @@ -39,10 +39,10 @@ define void @ashr_v4i32(<4 x i32> addrspace(1)* %out, <4 x i32> addrspace(1)* %i ret void } -;EG-CHECK: @ashr_i64 +;EG-CHECK-LABEL: @ashr_i64 ;EG-CHECK: ASHR -;SI-CHECK: @ashr_i64 +;SI-CHECK-LABEL: @ashr_i64 ;SI-CHECK: V_ASHR_I64 define void @ashr_i64(i64 addrspace(1)* %out, i32 %in) { entry: |