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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-14 23:24:32 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-14 23:24:32 +0000 |
| commit | 38d5e1c36d954f1ff6489f58efd1d4865217cf9b (patch) | |
| tree | 451454dd8bf6ea5ec2f3ea021da2c7f6de4a928a /test/CodeGen/R600/store.ll | |
| parent | 636298ba64fd07d4ddcae6005e7fc1db43eb5335 (diff) | |
| download | external_llvm-38d5e1c36d954f1ff6489f58efd1d4865217cf9b.zip external_llvm-38d5e1c36d954f1ff6489f58efd1d4865217cf9b.tar.gz external_llvm-38d5e1c36d954f1ff6489f58efd1d4865217cf9b.tar.bz2 | |
R600/SI: Lower BUILD_VECTOR to REG_SEQUENCE v2
Using REG_SEQUENCE for BUILD_VECTOR rather than a series of INSERT_SUBREG
instructions should make it easier for the register allocator to coalasce
unnecessary copies.
v2:
- Use an SGPR register class if all the operands of BUILD_VECTOR are
SGPRs.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188427 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/R600/store.ll')
| -rw-r--r-- | test/CodeGen/R600/store.ll | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/test/CodeGen/R600/store.ll b/test/CodeGen/R600/store.ll index 1bda5e6..506f0b0 100644 --- a/test/CodeGen/R600/store.ll +++ b/test/CodeGen/R600/store.ll @@ -26,7 +26,7 @@ define void @store_f32(float addrspace(1)* %out, float %in) { define void @store_v2f32(<2 x float> addrspace(1)* %out, float %a, float %b) { entry: %0 = insertelement <2 x float> <float 0.0, float 0.0>, float %a, i32 0 - %1 = insertelement <2 x float> %0, float %b, i32 0 + %1 = insertelement <2 x float> %0, float %b, i32 1 store <2 x float> %1, <2 x float> addrspace(1)* %out ret void } |