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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-16 01:11:46 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-16 01:11:46 +0000 |
| commit | e560d526a1aebf45e5333ab7b24689be930a8026 (patch) | |
| tree | 5ba5f513f854c36d3606b30655c4f482b7512a96 /test/CodeGen/R600/store.ll | |
| parent | 24ec2e5a72d7fca58f8ae2b3c01501a9927ef04e (diff) | |
| download | external_llvm-e560d526a1aebf45e5333ab7b24689be930a8026.zip external_llvm-e560d526a1aebf45e5333ab7b24689be930a8026.tar.gz external_llvm-e560d526a1aebf45e5333ab7b24689be930a8026.tar.bz2 | |
R600: Change the RAT instruction assembly names so they match the docs
Tested-by: Aaron Watry <awatry@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188515 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/R600/store.ll')
| -rw-r--r-- | test/CodeGen/R600/store.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/CodeGen/R600/store.ll b/test/CodeGen/R600/store.ll index 506f0b0..5dc0a84 100644 --- a/test/CodeGen/R600/store.ll +++ b/test/CodeGen/R600/store.ll @@ -4,9 +4,9 @@ ; floating-point store ; EG-CHECK: @store_f32 -; EG-CHECK: RAT_WRITE_CACHELESS_32_eg T{{[0-9]+\.X, T[0-9]+\.X}}, 1 +; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.X, T[0-9]+\.X}}, 1 ; CM-CHECK: @store_f32 -; CM-CHECK: EXPORT_RAT_INST_STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}} +; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD T{{[0-9]+\.X, T[0-9]+\.X}} ; SI-CHECK: @store_f32 ; SI-CHECK: BUFFER_STORE_DWORD @@ -17,9 +17,9 @@ define void @store_f32(float addrspace(1)* %out, float %in) { ; vec2 floating-point stores ; EG-CHECK: @store_v2f32 -; EG-CHECK: RAT_WRITE_CACHELESS_64_eg +; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW ; CM-CHECK: @store_v2f32 -; CM-CHECK: EXPORT_RAT_INST_STORE_DWORD +; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD ; SI-CHECK: @store_v2f32 ; SI-CHECK: BUFFER_STORE_DWORDX2 @@ -39,9 +39,9 @@ entry: ; be two 32-bit stores. ; EG-CHECK: @vecload2 -; EG-CHECK: RAT_WRITE_CACHELESS_64_eg +; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW ; CM-CHECK: @vecload2 -; CM-CHECK: EXPORT_RAT_INST_STORE_DWORD +; CM-CHECK: MEM_RAT_CACHELESS STORE_DWORD ; SI-CHECK: @vecload2 ; SI-CHECK: BUFFER_STORE_DWORDX2 define void @vecload2(i32 addrspace(1)* nocapture %out, i32 addrspace(2)* nocapture %mem) #0 { |