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| author | Tom Stellard <thomas.stellard@amd.com> | 2013-08-16 01:12:06 +0000 |
|---|---|---|
| committer | Tom Stellard <thomas.stellard@amd.com> | 2013-08-16 01:12:06 +0000 |
| commit | ec484277dd04399d7b2ea37508e39fc4998bc9a7 (patch) | |
| tree | 4a98a36ec60927ca4e52539ca15fed7754fe6660 /test/CodeGen/R600/store.ll | |
| parent | 4781d314b7b0bd239dc3986b4157726e80a270ba (diff) | |
| download | external_llvm-ec484277dd04399d7b2ea37508e39fc4998bc9a7.zip external_llvm-ec484277dd04399d7b2ea37508e39fc4998bc9a7.tar.gz external_llvm-ec484277dd04399d7b2ea37508e39fc4998bc9a7.tar.bz2 | |
R600: Add support for i16 and i8 global stores
Tested-by: Aaron Watry <awatry@gmail.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188519 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/R600/store.ll')
| -rw-r--r-- | test/CodeGen/R600/store.ll | 61 |
1 files changed, 61 insertions, 0 deletions
diff --git a/test/CodeGen/R600/store.ll b/test/CodeGen/R600/store.ll index f2a8dd7..cba01a3 100644 --- a/test/CodeGen/R600/store.ll +++ b/test/CodeGen/R600/store.ll @@ -2,6 +2,67 @@ ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck --check-prefix=CM-CHECK %s ; RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s +;===------------------------------------------------------------------------===; +; Global Address Space +;===------------------------------------------------------------------------===; + +; i8 store +; EG-CHECK: @store_i8 +; EG-CHECK: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X +; EG-CHECK: VTX_READ_8 [[VAL:T[0-9]\.X]], [[VAL]] +; IG 0: Get the byte index +; EG-CHECK: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x +; EG-CHECK-NEXT: 3 +; IG 1: Truncate the value and calculated the shift amount for the mask +; EG-CHECK: AND_INT T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], [[VAL]], literal.x +; EG-CHECK: LSHL * T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.y +; EG-CHECK: 255(3.573311e-43), 3 +; IG 2: Shift the value and the mask +; EG-CHECK: LSHL T[[RW_GPR]].X, PV.[[TRUNC_CHAN]], PV.[[SHIFT_CHAN]] +; EG-CHECK: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]] +; EG-CHECK-NEXT: 255 +; IG 3: Initialize the Y and Z channels to zero +; XXX: An optimal scheduler should merge this into one of the prevous IGs. +; EG-CHECK: MOV T[[RW_GPR]].Y, 0.0 +; EG-CHECK: MOV * T[[RW_GPR]].Z, 0.0 + +; SI-CHECK: @store_i8 +; SI-CHECK: BUFFER_STORE_BYTE + +define void @store_i8(i8 addrspace(1)* %out, i8 %in) { +entry: + store i8 %in, i8 addrspace(1)* %out + ret void +} + +; i16 store +; EG-CHECK: @store_i16 +; EG-CHECK: MEM_RAT MSKOR T[[RW_GPR:[0-9]]].XW, T{{[0-9]}}.X +; EG-CHECK: VTX_READ_16 [[VAL:T[0-9]\.X]], [[VAL]] +; IG 0: Get the byte index +; EG-CHECK: AND_INT * T{{[0-9]}}.[[BI_CHAN:[XYZW]]], KC0[2].Y, literal.x +; EG-CHECK-NEXT: 3 +; IG 1: Truncate the value and calculated the shift amount for the mask +; EG-CHECK: AND_INT T{{[0-9]}}.[[TRUNC_CHAN:[XYZW]]], [[VAL]], literal.x +; EG-CHECK: LSHL * T{{[0-9]}}.[[SHIFT_CHAN:[XYZW]]], PV.[[BI_CHAN]], literal.y +; EG-CHECK: 65535(9.183409e-41), 3 +; IG 2: Shift the value and the mask +; EG-CHECK: LSHL T[[RW_GPR]].X, PV.[[TRUNC_CHAN]], PV.[[SHIFT_CHAN]] +; EG-CHECK: LSHL * T[[RW_GPR]].W, literal.x, PV.[[SHIFT_CHAN]] +; EG-CHECK-NEXT: 65535 +; IG 3: Initialize the Y and Z channels to zero +; XXX: An optimal scheduler should merge this into one of the prevous IGs. +; EG-CHECK: MOV T[[RW_GPR]].Y, 0.0 +; EG-CHECK: MOV * T[[RW_GPR]].Z, 0.0 + +; SI-CHECK: @store_i16 +; SI-CHECK: BUFFER_STORE_SHORT +define void @store_i16(i16 addrspace(1)* %out, i16 %in) { +entry: + store i16 %in, i16 addrspace(1)* %out + ret void +} + ; floating-point store ; EG-CHECK: @store_f32 ; EG-CHECK: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+\.X, T[0-9]+\.X}}, 1 |