diff options
| author | Vincent Lejeune <vljn@ovi.com> | 2013-07-31 19:31:56 +0000 |
|---|---|---|
| committer | Vincent Lejeune <vljn@ovi.com> | 2013-07-31 19:31:56 +0000 |
| commit | 98ce62780ea7185ba710868bf83c8077e8d7f6d6 (patch) | |
| tree | 639ca4cbedb749ce5b4969fa112df1dbe35f6cd9 /test/CodeGen/R600/sub.ll | |
| parent | a92f8ee2f3ee12d26f6ed0720c763021cfa22ca8 (diff) | |
| download | external_llvm-98ce62780ea7185ba710868bf83c8077e8d7f6d6.zip external_llvm-98ce62780ea7185ba710868bf83c8077e8d7f6d6.tar.gz external_llvm-98ce62780ea7185ba710868bf83c8077e8d7f6d6.tar.bz2 | |
R600: Non vector only instruction can be scheduled on trans unit
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187514 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/R600/sub.ll')
| -rw-r--r-- | test/CodeGen/R600/sub.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/CodeGen/R600/sub.ll b/test/CodeGen/R600/sub.ll index 10fce6c..c7fed03 100644 --- a/test/CodeGen/R600/sub.ll +++ b/test/CodeGen/R600/sub.ll @@ -2,8 +2,8 @@ ;RUN: llc < %s -march=r600 -mcpu=verde | FileCheck --check-prefix=SI-CHECK %s ;EG-CHECK: @test2 -;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: SUB_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;SI-CHECK: @test2 ;SI-CHECK: V_SUB_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}} @@ -19,10 +19,10 @@ define void @test2(<2 x i32> addrspace(1)* %out, <2 x i32> addrspace(1)* %in) { } ;EG-CHECK: @test4 -;EG-CHECK: SUB_INT T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} -;EG-CHECK: SUB_INT * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} +;EG-CHECK: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}} ;SI-CHECK: @test4 ;SI-CHECK: V_SUB_I32_e32 VGPR{{[0-9]+, VGPR[0-9]+, VGPR[0-9]+}} |