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author | Stephen Hines <srhines@google.com> | 2014-12-01 14:51:49 -0800 |
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committer | Stephen Hines <srhines@google.com> | 2014-12-02 16:08:10 -0800 |
commit | 37ed9c199ca639565f6ce88105f9e39e898d82d0 (patch) | |
tree | 8fb36d3910e3ee4c4e1b7422f4f017108efc52f5 /test/CodeGen/R600/wait.ll | |
parent | d2327b22152ced7bc46dc629fc908959e8a52d03 (diff) | |
download | external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.zip external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.gz external_llvm-37ed9c199ca639565f6ce88105f9e39e898d82d0.tar.bz2 |
Update aosp/master LLVM for rebase to r222494.
Change-Id: Ic787f5e0124df789bd26f3f24680f45e678eef2d
Diffstat (limited to 'test/CodeGen/R600/wait.ll')
-rw-r--r-- | test/CodeGen/R600/wait.ll | 60 |
1 files changed, 34 insertions, 26 deletions
diff --git a/test/CodeGen/R600/wait.ll b/test/CodeGen/R600/wait.ll index 2cf88fe..735eabd 100644 --- a/test/CodeGen/R600/wait.ll +++ b/test/CodeGen/R600/wait.ll @@ -1,37 +1,45 @@ -; RUN: llc < %s -march=r600 -mcpu=SI --verify-machineinstrs | FileCheck %s +; RUN: llc -march=r600 -mcpu=SI -verify-machineinstrs < %s | FileCheck -strict-whitespace %s -;CHECK-LABEL: @main -;CHECK: S_WAITCNT lgkmcnt(0) -;CHECK: S_WAITCNT vmcnt(0) -;CHECK: S_WAITCNT expcnt(0) lgkmcnt(0) - -define void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, i32 inreg, i32, i32, i32, i32) #0 { +; CHECK-LABEL: {{^}}main: +; CHECK: s_load_dwordx4 +; CHECK: s_load_dwordx4 +; CHECK: s_waitcnt lgkmcnt(0){{$}} +; CHECK: s_waitcnt vmcnt(0){{$}} +; CHECK: s_waitcnt expcnt(0) lgkmcnt(0){{$}} +define void @main(<16 x i8> addrspace(2)* inreg %arg, <16 x i8> addrspace(2)* inreg %arg1, <32 x i8> addrspace(2)* inreg %arg2, <16 x i8> addrspace(2)* inreg %arg3, <16 x i8> addrspace(2)* inreg %arg4, i32 inreg %arg5, i32 %arg6, i32 %arg7, i32 %arg8, i32 %arg9, float addrspace(2)* inreg %constptr) #0 { main_body: - %10 = getelementptr <16 x i8> addrspace(2)* %3, i32 0 - %11 = load <16 x i8> addrspace(2)* %10, !tbaa !0 - %12 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %11, i32 0, i32 %6) - %13 = extractelement <4 x float> %12, i32 0 - %14 = extractelement <4 x float> %12, i32 1 - %15 = extractelement <4 x float> %12, i32 2 - %16 = extractelement <4 x float> %12, i32 3 - %17 = getelementptr <16 x i8> addrspace(2)* %3, i32 1 - %18 = load <16 x i8> addrspace(2)* %17, !tbaa !0 - %19 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %18, i32 0, i32 %6) - %20 = extractelement <4 x float> %19, i32 0 - %21 = extractelement <4 x float> %19, i32 1 - %22 = extractelement <4 x float> %19, i32 2 - %23 = extractelement <4 x float> %19, i32 3 - call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %20, float %21, float %22, float %23) - call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %13, float %14, float %15, float %16) + %tmp = getelementptr <16 x i8> addrspace(2)* %arg3, i32 0 + %tmp10 = load <16 x i8> addrspace(2)* %tmp, !tbaa !0 + %tmp11 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %tmp10, i32 0, i32 %arg6) + %tmp12 = extractelement <4 x float> %tmp11, i32 0 + %tmp13 = extractelement <4 x float> %tmp11, i32 1 + call void @llvm.AMDGPU.barrier.global() #1 + %tmp14 = extractelement <4 x float> %tmp11, i32 2 +; %tmp15 = extractelement <4 x float> %tmp11, i32 3 + %tmp15 = load float addrspace(2)* %constptr, align 4 ; Force waiting for expcnt and lgkmcnt + %tmp16 = getelementptr <16 x i8> addrspace(2)* %arg3, i32 1 + %tmp17 = load <16 x i8> addrspace(2)* %tmp16, !tbaa !0 + %tmp18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %tmp17, i32 0, i32 %arg6) + %tmp19 = extractelement <4 x float> %tmp18, i32 0 + %tmp20 = extractelement <4 x float> %tmp18, i32 1 + %tmp21 = extractelement <4 x float> %tmp18, i32 2 + %tmp22 = extractelement <4 x float> %tmp18, i32 3 + call void @llvm.SI.export(i32 15, i32 0, i32 0, i32 32, i32 0, float %tmp19, float %tmp20, float %tmp21, float %tmp22) + call void @llvm.SI.export(i32 15, i32 0, i32 1, i32 12, i32 0, float %tmp12, float %tmp13, float %tmp14, float %tmp15) ret void } +; Function Attrs: noduplicate nounwind +declare void @llvm.AMDGPU.barrier.global() #1 + ; Function Attrs: nounwind readnone -declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #1 +declare <4 x float> @llvm.SI.vs.load.input(<16 x i8>, i32, i32) #2 declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float) attributes #0 = { "ShaderType"="1" } -attributes #1 = { nounwind readnone } +attributes #1 = { noduplicate nounwind } +attributes #2 = { nounwind readnone } -!0 = metadata !{metadata !"const", null, i32 1} +!0 = metadata !{metadata !1, metadata !1, i64 0, i32 1} +!1 = metadata !{metadata !"const", null} |