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author | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2011-01-22 11:36:24 +0000 |
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committer | Venkatraman Govindaraju <venkatra@cs.wisc.edu> | 2011-01-22 11:36:24 +0000 |
commit | e105a3901fecce76e789566ecbfbc87a5b4ce899 (patch) | |
tree | 60ee0e8a5bbc2c503a7e640ea14f73c60123cb68 /test/CodeGen/SPARC/2011-01-11-CC.ll | |
parent | 0ef755d9051a79680326d6144a2401660fc93e57 (diff) | |
download | external_llvm-e105a3901fecce76e789566ecbfbc87a5b4ce899.zip external_llvm-e105a3901fecce76e789566ecbfbc87a5b4ce899.tar.gz external_llvm-e105a3901fecce76e789566ecbfbc87a5b4ce899.tar.bz2 |
Added ICC, FCC as uses of movcc instruction to generate correct code when -mattr=v9 is used.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124027 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SPARC/2011-01-11-CC.ll')
-rwxr-xr-x | test/CodeGen/SPARC/2011-01-11-CC.ll | 73 |
1 files changed, 51 insertions, 22 deletions
diff --git a/test/CodeGen/SPARC/2011-01-11-CC.ll b/test/CodeGen/SPARC/2011-01-11-CC.ll index 55d1764..3ceda95 100755 --- a/test/CodeGen/SPARC/2011-01-11-CC.ll +++ b/test/CodeGen/SPARC/2011-01-11-CC.ll @@ -1,11 +1,16 @@ -; RUN: llc -march=sparc <%s | FileCheck %s +; RUN: llc -march=sparc <%s | FileCheck %s -check-prefix=V8 +; RUN: llc -march=sparc -mattr=v9 <%s | FileCheck %s -check-prefix=V9 define i32 @test_addx(i64 %a, i64 %b, i64 %c) nounwind readnone noinline { entry: -; CHECK: addcc -; CHECK-NOT: subcc -; CHECK: addx +; V8: addcc +; V8-NOT: subcc +; V8: addx +; V9: addcc +; V9-NOT: subcc +; V9: addx +; V9: mov{{e|ne}} %icc %0 = add i64 %a, %b %1 = icmp ugt i64 %0, %c %2 = zext i1 %1 to i32 @@ -15,9 +20,13 @@ entry: define i32 @test_select_int_icc(i32 %a, i32 %b, i32 %c) nounwind readnone noinline { entry: -; CHECK: test_select_int_icc -; CHECK: subcc -; CHECK: {{be|bne}} +; V8: test_select_int_icc +; V8: subcc +; V8: {{be|bne}} +; V9: test_select_int_icc +; V9: subcc +; V9-NOT: {{be|bne}} +; V9: mov{{e|ne}} %icc %0 = icmp eq i32 %a, 0 %1 = select i1 %0, i32 %b, i32 %c ret i32 %1 @@ -26,9 +35,13 @@ entry: define float @test_select_fp_icc(i32 %a, float %f1, float %f2) nounwind readnone noinline { entry: -; CHECK: test_select_fp_icc -; CHECK: subcc -; CHECK: {{be|bne}} +; V8: test_select_fp_icc +; V8: subcc +; V8: {{be|bne}} +; V9: test_select_fp_icc +; V9: subcc +; V9-NOT: {{be|bne}} +; V9: fmovs{{e|ne}} %icc %0 = icmp eq i32 %a, 0 %1 = select i1 %0, float %f1, float %f2 ret float %1 @@ -36,9 +49,13 @@ entry: define double @test_select_dfp_icc(i32 %a, double %f1, double %f2) nounwind readnone noinline { entry: -; CHECK: test_select_dfp_icc -; CHECK: subcc -; CHECK: {{be|bne}} +; V8: test_select_dfp_icc +; V8: subcc +; V8: {{be|bne}} +; V9: test_select_dfp_icc +; V9: subcc +; V9=NOT: {{be|bne}} +; V9: fmovd{{e|ne}} %icc %0 = icmp eq i32 %a, 0 %1 = select i1 %0, double %f1, double %f2 ret double %1 @@ -46,9 +63,13 @@ entry: define i32 @test_select_int_fcc(float %f, i32 %a, i32 %b) nounwind readnone noinline { entry: -;CHECK: test_select_int_fcc -;CHECK: fcmps -;CHECK: {{fbe|fbne}} +;V8: test_select_int_fcc +;V8: fcmps +;V8: {{fbe|fbne}} +;V9: test_select_int_fcc +;V9: fcmps +;V9-NOT: {{fbe|fbne}} +;V9: mov{{e|ne}} %fcc0 %0 = fcmp une float %f, 0.000000e+00 %a.b = select i1 %0, i32 %a, i32 %b ret i32 %a.b @@ -57,9 +78,13 @@ entry: define float @test_select_fp_fcc(float %f, float %f1, float %f2) nounwind readnone noinline { entry: -;CHECK: test_select_fp_fcc -;CHECK: fcmps -;CHECK: {{fbe|fbne}} +;V8: test_select_fp_fcc +;V8: fcmps +;V8: {{fbe|fbne}} +;V9: test_select_fp_fcc +;V9: fcmps +;V9-NOT: {{fbe|fbne}} +;V9: fmovs{{e|ne}} %fcc0 %0 = fcmp une float %f, 0.000000e+00 %1 = select i1 %0, float %f1, float %f2 ret float %1 @@ -67,9 +92,13 @@ entry: define double @test_select_dfp_fcc(double %f, double %f1, double %f2) nounwind readnone noinline { entry: -;CHECK: test_select_dfp_fcc -;CHECK: fcmpd -;CHECK: {{fbne|fbe}} +;V8: test_select_dfp_fcc +;V8: fcmpd +;V8: {{fbne|fbe}} +;V9: test_select_dfp_fcc +;V9: fcmpd +;V9-NOT: {{fbne|fbe}} +;V9: fmovd{{e|ne}} %fcc0 %0 = fcmp une double %f, 0.000000e+00 %1 = select i1 %0, double %f1, double %f2 ret double %1 |