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| author | Hal Finkel <hfinkel@anl.gov> | 2013-04-13 23:06:15 +0000 |
|---|---|---|
| committer | Hal Finkel <hfinkel@anl.gov> | 2013-04-13 23:06:15 +0000 |
| commit | 63496f66c5b528a48f8da7714ee3f635f8aadd18 (patch) | |
| tree | f257ac7df6b506cbaa37cc6b5abfaf8bdddaf1c9 /test/CodeGen/SPARC/globals.ll | |
| parent | 41d59c61307002823c246c14589048266a6bf423 (diff) | |
| download | external_llvm-63496f66c5b528a48f8da7714ee3f635f8aadd18.zip external_llvm-63496f66c5b528a48f8da7714ee3f635f8aadd18.tar.gz external_llvm-63496f66c5b528a48f8da7714ee3f635f8aadd18.tar.bz2 | |
Mark all PPC CR registers to be spilled as live-in and tag MFCR appropriately
Leaving MFCR has having unmodeled side effects is not enough to prevent
unwanted instruction reordering post-RA. We could probably apply a stronger
barrier attribute, but there is a better way: Add all (not just the first) CR
to be spilled as live-in to the entry block, and add all CRs to the MFCR
instruction as implicitly killed.
Unfortunately, I don't have a small test case.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179465 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SPARC/globals.ll')
0 files changed, 0 insertions, 0 deletions