diff options
| author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-07-11 08:59:12 +0000 |
|---|---|---|
| committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-07-11 08:59:12 +0000 |
| commit | b3cabb44c32b5a3aba9b4d23aae9723d498ea7a9 (patch) | |
| tree | 67565add4984989a53566cb7836cfadc52f2e39e /test/CodeGen/SystemZ/addr-01.ll | |
| parent | 3ee0673e4f5f0324ecd0a65507009b0748ed072c (diff) | |
| download | external_llvm-b3cabb44c32b5a3aba9b4d23aae9723d498ea7a9.zip external_llvm-b3cabb44c32b5a3aba9b4d23aae9723d498ea7a9.tar.gz external_llvm-b3cabb44c32b5a3aba9b4d23aae9723d498ea7a9.tar.bz2 | |
[SystemZ] Use zeroing form of RISBG for some AND sequences
RISBG can handle some ANDs for which no AND IMMEDIATE exists.
It also acts as a three-operand AND for some cases where an
AND IMMEDIATE could be used instead.
It might be worth adding a pass to replace RISBG with AND IMMEDIATE
in cases where the register operands end up being the same and where
AND IMMEDIATE is smaller.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@186072 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SystemZ/addr-01.ll')
| -rw-r--r-- | test/CodeGen/SystemZ/addr-01.ll | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/test/CodeGen/SystemZ/addr-01.ll b/test/CodeGen/SystemZ/addr-01.ll index c125ffa..bf2ad7b 100644 --- a/test/CodeGen/SystemZ/addr-01.ll +++ b/test/CodeGen/SystemZ/addr-01.ll @@ -65,8 +65,8 @@ define void @f5(i64 %addr, i64 %index) { ; An address with an index and a displacement added using OR. define void @f6(i64 %addr, i64 %index) { ; CHECK: f6: -; CHECK: nill %r2, 65528 -; CHECK: lb %r0, 6(%r3,%r2) +; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0 +; CHECK: lb %r0, 6(%r3,[[BASE]]) ; CHECK: br %r14 %aligned = and i64 %addr, -8 %or = or i64 %aligned, 6 @@ -93,10 +93,10 @@ define void @f7(i64 %addr, i64 %index) { ; about the alignment of %add here. define void @f8(i64 %addr, i64 %index) { ; CHECK: f8: -; CHECK: nill %r2, 65528 -; CHECK: agr %r2, %r3 -; CHECK: oill %r2, 6 -; CHECK: lb %r0, 0(%r2) +; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0 +; CHECK: agr [[BASE]], %r3 +; CHECK: oill [[BASE]], 6 +; CHECK: lb %r0, 0([[BASE]]) ; CHECK: br %r14 %aligned = and i64 %addr, -8 %add = add i64 %aligned, %index |