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authorRichard Sandiford <rsandifo@linux.vnet.ibm.com>2013-07-31 11:36:35 +0000
committerRichard Sandiford <rsandifo@linux.vnet.ibm.com>2013-07-31 11:36:35 +0000
commitb3f912b510f8040690864126351b7021980558bb (patch)
treeb767382a270aba304d043390e89558e023b63c6d /test/CodeGen/SystemZ/addr-01.ll
parent8395251c0a1f16531e7f4d11a766a4a1e3d25520 (diff)
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[SystemZ] Postpone NI->RISBG conversion to convertToThreeAddress()
r186399 aggressively used the RISBG instruction for immediate ANDs, both because it can handle some values that AND IMMEDIATE can't, and because it allows the destination register to be different from the source. I realized later while implementing the distinct-ops support that it would be better to leave the choice up to convertToThreeAddress() instead. The AND IMMEDIATE form is shorter and is less likely to be cracked. This is a problem for 32-bit ANDs because we assume that all 32-bit operations will leave the high word untouched, whereas RISBG used in this way will either clear the high word or copy it from the source register. The patch uses the z196 instruction RISBLG for this instead. This means that z10 will be restricted to NILL, NILH and NILF for 32-bit ANDs, but I think that should be OK for now. Although we're using z10 as the base architecture, the optimization work is going to be focused more on z196 and zEC12. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187492 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test/CodeGen/SystemZ/addr-01.ll')
-rw-r--r--test/CodeGen/SystemZ/addr-01.ll12
1 files changed, 6 insertions, 6 deletions
diff --git a/test/CodeGen/SystemZ/addr-01.ll b/test/CodeGen/SystemZ/addr-01.ll
index cf4ed89..d0960cd 100644
--- a/test/CodeGen/SystemZ/addr-01.ll
+++ b/test/CodeGen/SystemZ/addr-01.ll
@@ -65,8 +65,8 @@ define void @f5(i64 %addr, i64 %index) {
; An address with an index and a displacement added using OR.
define void @f6(i64 %addr, i64 %index) {
; CHECK-LABEL: f6:
-; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
-; CHECK: lb %r0, 6(%r3,[[BASE]])
+; CHECK: nill %r2, 65528
+; CHECK: lb %r0, 6(%r3,%r2)
; CHECK: br %r14
%aligned = and i64 %addr, -8
%or = or i64 %aligned, 6
@@ -93,10 +93,10 @@ define void @f7(i64 %addr, i64 %index) {
; about the alignment of %add here.
define void @f8(i64 %addr, i64 %index) {
; CHECK-LABEL: f8:
-; CHECK: risbg [[BASE:%r[1245]]], %r2, 0, 188, 0
-; CHECK: agr [[BASE]], %r3
-; CHECK: oill [[BASE]], 6
-; CHECK: lb %r0, 0([[BASE]])
+; CHECK: nill %r2, 65528
+; CHECK: agr %r2, %r3
+; CHECK: oill %r2, 6
+; CHECK: lb %r0, 0(%r2)
; CHECK: br %r14
%aligned = and i64 %addr, -8
%add = add i64 %aligned, %index